Hello, I have a project that can do; It accomplishes all of this perfectly. Now

Question

Hello,

I have a project that can do;

It accomplishes all of this perfectly. Now I need to edit the program in a way that it multiplies 2 numbers instead of add them. I need to do this with arithmetic operator which is * symbol (verilog accepts it) However I got stuck because my ALU doesnt use + symbol so its not as easy as changing operator (it was what i was told that :( ) I dont the program to add anymore, just multiply. Here are some screenshots from my ALU code.

So to make long story short, I need the adder to be a multipler of 2 numbers. I was told that it would be very easy due to changing the operator however given ALU code is not written with operators ! Otherwise it would have been easier as he mentioned.

This is the sketch of what my project does right now;

Here is link to my project;

https://onedrive.live.com/redir?resid=8046006B5C97DF56%21478

Let me know if you have a question about it.

Thanks

Explanation / Answer

ANSWER:

Use the following code to multiply 2 4-bit numbers. The mutiplier was made using half and full adders.

module HA(sout,cout,a,b);
output sout,cout;
input a,b;
assign sout=a^b;
assign cout=(a&b);
endmodule

module FA(sout,cout,a,b,cin);
output sout,cout;
input a,b,cin;
assign sout=(a^b^cin);
assign cout=((a&b)|(a&cin)|(b&cin));
endmodule

module multiply4bits(product,inp1,inp2);
output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;
assign product[0]=(inp1[0]&inp2[0]);
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
FA FA1(x2,x3,inp1[1]&inp2[1],(inp1[0]&inp2[2]),x1);
FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);
endmodule

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