. Reinforce understanding of combinational logic design and the design process.
ID: 2991022 • Letter: #
Question
. Reinforce understanding of combinational logic design and the design process. . Practice combining models in Verilog to create complex designs. Overview In this project you will write and simulate a Verilog program that implements the S -bit ALU shown in Figure 1. The ALU will perform the operations listed in the table below. Procedure: 1. Design the ALU shown in Figure 1, use any components you need (refer to figure 1 for inputs and outputs). The ALU should work as indicated in the table above (if select is 000 the output should be A, if select is 001, output should be B. etc). 2. Use Logisim to implement your design and simulate it. 3. Using Verilogger (or any other Verilog simulator) create a top model to implement the ALU. Describe the ALU using behavioral modeling. You can modify and use any of the modules you have created in lab 6 and Lab 7 to aid in your design. You can simply add the Verilog files to your design and instantiate the required components. 4. Create a test module to simulate your code. Your test bench should include all 8 functions.Explanation / Answer
Hey sir, i am writing with 4 bit, please change accordingly
module alu(a,b,cin,alu,carry,zero,ctl);
input [3:0] a,b; // port A,B
input cin ; // carry input from carry flag register
output [3:0] alu; // the result
output carry; // carry output
output zero ; // zero output
input [3:0] ctl ; // functionality control for ALU
wire [4:0] result; // ALU result
assign result = alu_out(a,b,cin,ctl);
assign alu = result[3:0];
assign carry = result[4] ;
assign zero = z_flag(result) ;
function [4:0] alu_out;
input [3:0] a,b ;
input cin ;
input [3:0] ctl ;
case ( ctl )
4'b0000: alu_out=b; // select data on port B
4'b0001: alu_out=b+4'b0001 ; // increment data on port B
4'b0010: alu_out=b-4'b0001 ; // decrement data on port B
4'b0011: alu_out=a+b; // ADD without CARRY
4'b0100: alu_out=a+b+cin; // ADD with CARRY
4'b0101: alu_out=a-b ; // SUB without BORROW
4'b0110: alu_out=a-b+(~cin); // SUB with BORROW
4'b0111: alu_out=a&b; // AND
4'b1000: alu_out=a|b; // OR
4'b1001: alu_out=a^b; // EXOR
4'b1010: alu_out={b[3:0],1'b0}; // Shift Left
4'b1011: alu_out={b[0],1'b0,b[3:1]}; // Shift Right
4'b1100: alu_out={b[3:0],cin}; // Rotate Left
4'b1101: alu_out={b[0],cin,b[3:1]}; // Rotate Right
default : begin
alu_out=9'bxxxxxxxxx;
$display("Illegal CTL detected!!");
end
endcase /* {...,...,...} is for the concatenation.
{ADD_WITH_CARRY,SUB_WITH_BORROW}==2'b11 is used
to force the CARRY==1 for the increment operation */
endfunction // end of function "result"
function z_flag ;
input [4:0] a4 ;
begin
z_flag = ^(a4[0]|a4[1]|a4[2]|a4[3]) ; // zero flag check for a4
end
endfunction
endmodule
Related Questions
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.