7. The following circuit has one input: clock and four outputs: QO. Ql. A2. Q3 I
ID: 2991043 • Letter: 7
Question
7. The following circuit has one input: clock and four outputs: QO. Ql. A2. Q3 It has four T -flip-flops. The T -flip-flop function description in VHDI. is given in the following. The gate of and may use operators and Write a structural style VHDL program (with entity and architecture) to describe the circuits. (20 points) library ieee: use ieee.std_logic_1164.all; entity T_FF is port (T, Clock : in std_loipc; 0. Qbar : out std_logic); end entity T_FF; architecture var of T_FF is begin p0. process (Clock) is variable state: std_logic; begin if rising_edge(Clock) then if T = '1 then state := not state; end if; end if; QExplanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tffl is
port(t,rst,clk:in std_logic;
q,qb:out std_logic);
end tffl;
architecture Behavioral of tffl is
begin
process
variable x:std_logic:='0';
begin
wait on clk ;
if (clk' event and clk='1') then
if rst='1' then
x:='0';
elsif t='1' then
x:=not x;
else
x:=x;
end if;
end if;
q<=x;
qb<=not x;
end process;
end Behavioral;
--code for counter:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tcounter is
port(clk,rst:in std_logic;
q,qbar:inout std_logic_vector(3 downto 0));
end tcounter;
architecture Behavioral of tcounter is
component tffl is
port(t,rst,clk:in std_logic;
q,qb:out std_logic);
end component;
signal k,l,m:std_logic;
begin
k<=q(0);
l<=q(0) and q(1);
m<=q(0) and q(1) and q(2);
a1:tffl port map('1',rst,clk,q(0),qbar(0));
a2:tffl port map(k,rst,clk,q(1),qbar(1));
a3:tffl port map(l,rst,clk,q(2),qbar(2));
a4:tffl port map(m,rst,clk,q(3),qbar(3));
end Behavioral;
one more way:
--libraries to be used are specified here
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--entity declaration with port definitions
entity syn_count4 is
port ( clk: in std_logic;
reset: in std_logic;
counter : out std_logic_vector(3 downto 0)
);
end syn_count4;
--architecture of entity
architecture Behavioral of syn_count4 is
--signal declaration.
signal J3,J4,Q1,Q2,Q3,Q4,Qbar1,Qbar2,Qbar3,Qbar4 : std_logic :='0';
begin
J3 <= Q1 and Q2;
J4<= J3 and Q3;
--entity instantiations
FF1 : entity work.JK_Flipflop port map (clk,'1','1',Q1,Qbar1,reset);
FF2 : entity work.JK_Flipflop port map (clk,Q1,Q1,Q2,Qbar2,reset);
FF3 : entity work.JK_Flipflop port map (clk,J3,J3,Q3,Qbar3,reset);
FF4 : entity work.JK_Flipflop port map (clk,J4,J4,Q4,Qbar4,reset);
counter <= Q4 & Q3 & Q2 & Q1;
end Behavioral;
The test bench program used for testing the design is given below:
--libraries to be used are specified here
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity testbench is
end testbench;
architecture behavior of testbench is
--Signal declarations
signal clk,reset : std_logic := '0';
signal counter : std_logic_vector(3 downto 0):="0000";
-- Clock period definitions
constant clk_period : time := 1 ns;
begin
-- Instantiate the Unit Under Test (UUT)
UUT : entity work.syn_count4 port map (clk,reset,counter);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period*20;
reset <='1';
wait for clk_period*2;
reset <='0';
end process;
end;
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