This is the code for the previous step: module counter(input clk,input rst,input
ID: 2991212 • Letter: T
Question
This is the code for the previous step:
module counter(input clk,input rst,input enable,input up_down, output reg [6:0] counter_output);
initial counter_output = 7'b1011010;
always@ (posedge clk)
begin
if( rst | counter_output==7'b1011010 | counter_output == 7'b1101110)
if(counter_output == 7'b1101110)
counter_output <= 5'b1011010;
if(counter_output == 7'b1011010)
counter_output <= 5'b1101110;
else if(enable)
counter_output <= up_down ? counter_output + 1 : counter_output - 1 ;
end
endmodule
(c) Modify the program so that when the counter is counting up it should count up from -30 to +30 continuously and when it is counting down it should count down from +30 to -30 continuously. Each count increment should occur after every 0.5 seconds. (d) For part (c) show the binary representation of the count on the 8 LEDs with the most significant bit as the sign bit. So if the counter is at -8 the LED should be showing 10000111 and when it is +8 it should be showing 00000111. In this part each count increment/decrement should occur after every 1 second.Explanation / Answer
module counter(input clk,input rst,input enable,input up_down, output reg [6:0] counter_output);
initial counter_output = 7'b1011010;
always@ (posedge clk)
begin
if( rst | counter_output==7'b1011010 | counter_output == 7'b1101110)
if(counter_output == 7'b1101110)
counter_output <= 5'b1011010;
if(counter_output == 7'b1011010)
counter_output <= 5'b1101110;
else if(enable)
counter_output <= up_down ? counter_output +30 : counter_output - 30 ;
end
endmodule
Related Questions
drjack9650@gmail.com
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.