7.1 For the microprogrammed architecture of Figure P 7.1, give the sequence of a

Question

7.1 For the microprogrammed architecture of Figure P 7.1, give the sequence of actions required to implement the instructions ADD D0, D1 which is defined in RTL as [D1] <— [D1] + [D0].
You should describe the actions that occur in plain English and as a sequence of events. The following table defines the effect of the ALU’s function code. Note that all data has to pass through the ALU to get from bus B or bus C to bus A.

7.2 For the architecture of Figure P 7.1, write the sequence of signals and control actions necessary to implement the fetch cycle.
Chapter 7 Processor Control Problems For the architecture of Figure PZI, TI give the o"..the sequence of actions required to implement the instruction ADD DO, D which is defined in truction, AOD Do, D1 whichs defined in RTL as RTL as 0 00 Copy P to bus A should describe the actions that occur in plain 011 Cop+ I to bus A A-0+1 A- P A Q 0 1 0 Copy P+1 to bus A and as a sequence of events (e, Read-1, Esa)The (eg."Put data from this register on that bus") 1 0 0 A P+ Copy P-1to bus A AP-1 01 Copy 0-1 to bus A A Q-1 table defines the effect of the ALU's function 1 code. Note (the copy function) to get from bus B or bus Cto bus.A. 1 e that all data has to pass through the ALU 1 1 0 1 1 Copy bus P+ Q to bus A Copy bus P- A-P+Q to buS A A-P-Q FIGURE P7.1 Architecture of a hypothetical computer Bus A Bus B Read Write Main sore Euan The memory peforms Data in a read when Read- and a write when Write 1 MAR MBRQm IR PC Do D1 ALU atch 1 Latch 2 Figure P21 so signals and control actions necessary to imple- ment the fetch cycle. 75 For the architecture of Figure P21,write the sequence of signals and control actions necessary to execute For the architecture of Figure PZI write the sequence 24 Why is the ALU instruction set of of Why is the structure of Figure PZl so inefficient?

Explanation / Answer

1. The control unit generates the signal for sequencing the operation in datapath.

2. Using status conditions and control input, the sequential control unit determines the next state in which additional micro operations are operated.

3. controller function include

a. Fetch cycle- Generates the control signal to fetch instruction from memory and sequence of operations involved in processing instruction.

b. Execution cycle- It involve interpreting the operand addressing mode implied in the operation code and fetching the operands and sequencing the successive microoperations on the data path to execute the operation code specified in the instruction.

CPU fetches and execute each instructions of the program.

Successively goes through fetch , execute cycles

4. PC holds the address of the instruction to be executed.

5. During fetch cycle PC is incremented to hold the address of the next instruction.

6. Assuming each instruction has the length of one word the PC is incremented by 1 PC<= PC + 1

E F Comment 0 0 Not used 0 1 Fetch Cycle 1 0 Execute cycle 1 1 Intrupt cycle

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