Design using a combinational VHDL process a sign magnitude to two’s complement c
ID: 3348980 • Letter: D
Question
Design using a combinational VHDL process a sign magnitude to two’s complement converter
using the given algorithm and hardware description. Use the following VHDL entity specifica-
tion:
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity converter is
port( sign_mag : in std_logic_vector(3 downto 0) ;
twos_comp : out std_logic_vector(3 downto 0) );
end;
The following algorithm may be used to convert from sign-magnitude into two’s complement rep-
resentation:
if (the input is a positive number) then
{
the output is the same as the input
}
else
{
negate the magnitude bits of the input;
add “001” to the negated magnitude bits to obtain
the low order bits of the output ;
set the high order bit of the output to the high order bit of the input
}
Some Hints
• Make use vector slices (array manipulation) and the concatenation operator to gain access to
the magnitude bits and to form the output signal.
• You are free to make use of variables or to write the process making use of only signals.
Value isValue in 2's Input Output sign magnitude complement 0001 0010 0011 0100 0101 0110 0111 1000 0001 0010 0011 0100 0101 0110 0111 1000 -0 Table 1: Sign-Magnitude and 2's complement representation Value isValue in 2's Input Output sign magnitude complement 1001 010 1011 1100 1101 1110 1110 1101 1100 1011 010 1001 -6 -6Explanation / Answer
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity converter is
port( sign_mag : in std_logic_vector(3 downto 0) ;
twos_comp : out std_logic_vector(3 downto 0) );
end;
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