Hello, I need some help troubleshooting my code.. Here is my assignment: Sixteen

Question

Hello,

I need some help troubleshooting my code..

Here is my assignment:

Sixteen Bit Register with Load and Shift: Implement all 16-bits in a single VHDL process.When the load signal is asserted, the register should synchronously load the value of din.When shift = ‘1’, bit 15 should load zero and bits (14:0)should be assigned to the previous value of bits(15:1).

Here is my code:

Here is my testbench:

As you can see, in my testbench, I get syntax errors at lines 45 and 49. Could someone help me with this?

Thanks!

library IEEE: use IEEE.std logic 1164.all; entity sbsr 1s is port ( clock : in std logic; load shift din dout : in std logic; : in std logic; :in std_logic_vector (15 downto 0) :out stdlogic_vector (15 downto 0)): end sbsr ls architecture arch of sbsr ls is begin process (clock) begin if (rising edge (clock)) then if (load = ' I ') then dout

Explanation / Answer

library ieee;
use ieee.std_logic_1164.all;

entity sbsr_ls is
port ( clock : in std_logic;
  load : in std_logic;
  shift : in std_logic;
  din : in std_logic_vector (15 downto 0);
  dout : out std_logic_vector (15 downto 0));
end sbsr_ls;

architecture arch of sbsr_ls is
signal dout_reg : std_logic_vector (15 downto 0);
begin

process (clock)
begin
if (rising_edge (clock)) then
  if (load = '1') then
   dout_reg <= din;
  end if;
end if;
end process;

process(clock)
begin
if (rising_edge (clock)) then
  if (shift = '1') then
   dout_reg <= '0' & dout_reg (15 downto 1); --- a reg is defined as dout is a output port and can not be a input
  end if;
end if;
end process;
dout <= dout_reg;
end arch;

-------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity sbsr_ls_tb is
end sbsr_ls_tb;

architecture arch of sbsr_ls_tb is

component sbsr_ls is
port ( clock : in std_logic;
  load : in std_logic;
  shift : in std_logic;
  din : in std_logic_vector (15 downto 0);
  dout : out std_logic_vector (15 downto 0));
end component;

signal clock : std_logic;
signal load : std_logic;
signal shift : std_logic;
signal din : std_logic_vector (15 downto 0);
signal dout : std_logic_vector (15 downto 0);

begin

uut: sbsr_ls port map (clock => clock,
                       load => load,
                       shift => shift,
                       din => din,
                       dout => dout);

stimulus: process
begin
shift <= '1';
din <= x"0000"; -- vector is double quoted and its a 16 bit number. use x as a hex decimal number representation
wait for 20 ns;
shift <= '0';
wait for 300 ns;
din <= x"0001";   -- vector is double quoted
wait;
end process;

clocking: process
begin
clock <= '0';
wait for 10 ns;
clock <= '1';
wait for 10 ns;
end process;
end arch;

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