The answer is already given, but I want you to explain why, thank you Question 9

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The answer is already given, but I want you to explain why, thank you Question 9 (1 point) Assume we need to design a software program to implement edge-triggered interrupts. In the system, the input port PD2 is connected with an external switch si using positive logic. When SI is pressed, no interrupt will be generated. When SI is released, an edge-triggered interrupt will be triggered. Assume there is no switch bouncing. Given these requirements, the IS, IBE, IEV, and IME bits need to be configured as answer in the box. to implement the interrupt. Put the A. 0, 0, 0, 0 B. 0, 1, 0, 1 C. 0, 0, 1, 1 D. 0, 0, 0, 1 Question 10 (1 point) To configure the interrupt priority of interrupt vector ADCO Sequence 2, which NVIC priority register needs to be configured? Put the answer in the box. A. NVIC PRI7R B. NVIC_PRI8R C. NVIC PRI3 R D. NVIC_PRI4 R

Explanation / Answer

9.

To configure Edge triggered interrupt input, it is required to enable clock and intended pin as digital input.

Interrupt Sense (IS) bit – is 0 for edge trigger / 1 for level trigger

Interrupt Both Edges (IBE) and Interrupt Event (IEV) – These two bits are used to define the active edges (i.e. rising edge / falling edge / Both Edges).

IBE

IEV

Sensitive

0

0

Falling edge

0

1

Rising edge

1

-

Both Edge

IME is 0 for busy wait / 1 for Interrupt

IS

IBE

IEV

IME

PORT Mode

0

0

0

1

Input Mode, Falling Edge trigger, Interrupt

10.

Interrupts on Cortex are controlled by Nested Vectored Interrupt Controller (NVIC). Each Exception (i.e. interrupt) corresponds to 32-bit address vector in a memory where its ISR is stored.

Hence we can identify using datasheet that ADC0Seq2_Handler is located at 0x00000080 address.

On 0x00000080 address, ADC_Handler resides with register NVIC_PRI4_R with bits 7-5 in NVIC controller is used to enable and set priority of ADC0Seq2 interrupt.

IBE

IEV

Sensitive

0

0

Falling edge

0

1

Rising edge

1

-

Both Edge

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