I need help for code for my SystemVeriglog code (not VHDL) module workSheet2ALU(
ID: 3349336 • Letter: I
Question
I need help for code for my SystemVeriglog code (not VHDL)
module workSheet2ALU( input logic signed [7:0] a,b,
input logic btnU, btnL, btnC, btnR, btnD,
output logic [7:0] led );
// write the logic for the ALU here
// up button should correspond to a + b
// left button should correspond to a XOR b
// center button should correspond to 8'b0000_0001 if a < b, 8'b0000_0000 otherwise
// right button should correspond to arithmetic right shift by 2
// down button should correspond to a - b
// the output of the ALU should be assigned to led, which maps to the rightmost 8 leds on your BASYS3
// (this mapping has already been done in Basys3_Master.xdc)
endmodule
Explanation / Answer
module workSheet2ALU (
input [7:0] a,b, //inputs to alu
input [3:0] opcode, //control signal for different operation
output reg [7:0] led ); //op of alu
parameter [2:0] btnU = 3'b000,
btnL = 3'b001,
btnC = 3'b010,
btnR = 3'b011,
btnD = 3'b100;
always @(a or b or opcode)
begin
case (opcode)
3'b000 : begin
led = a + b; //"Addition operation
end
3'b001 : begin
led = a ^ b; //Bit-wise XOR operation
end
3'b010 :
begin
if(a<b)
led = 8'b0000_0001;
else
led = 8'b0000_0000;
end
3'b011 : begin
led = a >> 2; //Right Shift by 2 operation
end
3'b100 : begin
led = a - b; //Subtraction Operation
end
default:led = 8'bXXXXXXXX;
endcase
end
endmodule
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