PROBLEM 5: (20 pts) Given the figure and System Verilog code below, answer the f

Question

PROBLEM 5: (20 pts) Given the figure and System Verilog code below, answer the followinsg questions about the recister ile. nodule regtileCinput logic clk, input 1ogie 3, iaput logic (3:)rai, ra2, wa3, input logic t3i:0] was, r15, output logic (31:0) rd1, rd2) CLK A1 WES A2 RD1 logic (31:0) rtt1s:o) RD2 always.ff (posedge clk) - Register WD3Fille R15 entnodule Part A (5 pts) List the input values that would allow R10 to be read. Put an "X" for the value of inputs that do not matter. ral ra2 = r15 clk Part B (5 pts) How many bits is WD3 Part C (5 pts) List the input values that would allow R12 to be written to. Put an "X" for the value of inputs that do not matter. ra2 ra3 . we3 Part D (5 pts) List the output values that would occur if ral 5, ra2 - 3, ra3 6, wd3 1527, r15 10000, and we -0. Assume the clock has received the appropriate inputs for 1 clock cycle. Page 6 of 8

Explanation / Answer

module register_file (
input logic          clk, // clock input
input logic          we3, // write enable
input logic [3:0]   ra1, // read address 1
input logic [3:0]   ra2, // read address 2
input logic [3:0]   wa3, // write address
input logic [31:0] wd3, // write data
input logic [31:0] r15, // register 15 data seperately
output logic [31:0] rd1, // read data at address 1
output logic [31:0] rd2   // read data at address 2
);

// defining register from r0 to r14 each of 32 bit wide
logic [31:0] rf[14:0];

always_ff (posedge clk)
if (we3) rf[wa3] <= wd3; // write input data wd3 at address wa3 when write enable is 1

// read data from address specified by ra1 (read address 1)
assign rd1 = (ra1 == 4'b1111) ? r15 : rf[ra1];

// read data from address specified by ra2 (read address 2)
assign rd2 = (ra2 == 4'b1111) ? r15 : rf[ra2];

endmodule

Note :: This module is used to read two register and write another register at a time;

i.e Two read and single write can be performed by this module

-------------
| Part A) |
-------------
We assume that only we need register r10 data at port rd1.

So, to read data from R10 register we need (read address 1) ra1 = 1010 and others bits as don't care
i.e
ra1 = "4'b1010" ; ra2 = 'x' ; wa3 = 'x' ; wd3 = 'x' ; r15 = 'x' ; we3 = 'x' ; clk = 'x'

-------------
| Part B) |
-------------
WD3 is 32 bits wide; as mentioned in port definition as input logic [31:0] wd3

-------------
| Part C) |
-------------

Assume write data = 32'h1234_5678;

So, to write data to R12 register we need (write address) wa3 = '1100', along
with (write data) wd3 == "32'h 1234_5678" and write enable = '1' at posedge of clk
and other bits as don't care
i.e
ra1 = 'x' ; ra2 = 'x' ; wa3 = "4'b1100"; wd3 = "32'h1234_5678" ; r15 = 'x' ; we3 = '1'b1' ; clk = positive edge;

-------------
| Part D) |
-------------
Given condition
ra1 = 5 ; ra2 = 3 ; wa3 = 6 ; wd3 = 1527 ; r15 = 1000000 ; we3 = '0' ; clk = positive edge;

as Write Enable we3 = '0' therefore no write operation will be performed and hence,
wd3 and wa3 are not taken into consideration

rd1 = register R5 data is present at output rd1
rd2 = register R3 data is present at output rd2

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