Worked out solutions please Consider a processor which uses 16 bit addresses and

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Worked out solutions please

Consider a processor which uses 16 bit addresses and can address 2 16=64K bytes of memory. Suppose that it has one level of cache. As in Figure 6.27 of your textbook, the address is split into a t bit tag, an s bit set index, and a b bit block offset. The cache consists of 1024 bytes, with a block size of 64 bytes. Answer each of the following for direct-mapped, 4-way set associative, and fully associative versions of the cache. How many cache lines are there? What is b? What is s? What is t? For the cache in problem 3, draw the cache given it is structured as follows. You can elide replicated components, but annotate your drawing with how many components there are. Direct-mapped 4-way set associative Fully associative Our company wants to optimize the performance of the following code run on the same processor and cache as described in problem 3. The cache is write-back, write-allocate, and has an LRU replacement policy. Integers are 32 bits. Suppose the cache is direct mapped. Let n=2048, a=0x4000, b=0x8000, c=0xc000. On average, how many times per loop iteration will you load a cache block from main memory? How many times per loop iteration will you flush a cache block back to main memory? What is the minimum degree of associativity (i.e., the n in n-way) that the cache needs to reduce the answers in (a) to 0.25 cache blocks read per iteration and 0.125 cache blocks Written per iteration? While we're all fired up to buy ultra-cool mega-associative cache hardware (which comes only in machined aluminum), a smart alec programmer claims that we can get the same effect by having a=0x4000, b=0x8020, and c=0xc040. Is he right? Why or why not?

Explanation / Answer

I kw the ans of 1 que. Second que i am not able to understand what it saying can u explain in a

Simple then i will try to give ans. For last i am geting ans but hve sm doubts thats why i am not posting

For the 1 que

block size 64 Bytes =2^6

cache size 1024 Byte =2^10

in cache no of block = 2^10/2^6 = 2^6

16 bit--> first 4 bit for block no and remaining 6 bits for block offfset.

In system 16 bit address

Last 6 bit for offset so b=6bit.

A) Direct Mapping

no of block in cache = 2^4

so 16 bit is divided as follow

16bit--> 6bits(TAG)+4bits(Block No)+6bits(Offset)

b=6,s=4,t=6.

B) 4 way associative mapping

in one set 4 block

so no of set in cahce = 2^4/2^2=2^2

so 16 bit is divided as follow

16bit--> 8bits(TAG)+2bits(Set No)+6bits(Offset)

b=6,s=2,t=8.

so 16 bit is divided as follow

16bit--> 10bits(TAG)+6bits(Offset)

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