1.Why the hardwired zero register is important in RISC architectures? 2.The, MIP

Question

1.Why the hardwired zero register is important in RISC architectures?

2.The, MIPS, ISA, does not include a negate, instruction. Provide, another ,MIPS assembly instruction that negates the contents of register, 3 and, writes the result ,into register, 4.?

3.Is it more, important ,to include a floating-poin,t multiplication instruction, or an integer m,ultiplication, instruction in the ISA, of a new processor, family, and why?

4.Comput,e the addres,s from which the load, byte, instruction, below reads, the address to which the ,branch transfers control, if, taken, and the address that is the target of the jump ,in-struction.

0x80000000: lui $t2, 1

0x80000004: lb $t3, 1($t2)

0x80000008: beq $t3, $zero, 1

0x8000000C: j 1

5. how the effectiv,e address of a ,load, or store, instructio,n is computed ,in, MIPS?

Explanation / Answer

1-ANS-

There are currently a significant (though arguably falling

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