In this exercise, we will look at how a common vector loop runs on statically an

Question

In this exercise, we will look at how a common vector loop runs on statically and dynamically scheduled versions of the MIPS pipeline. The loop is the so-called DAXPY loop and the central operation in Gaussian elimination. The loop implements the vector operation Y = a * X + Y for a vector of length 100. Here is the MIPS code for the loop:

For parts (a) to (c), assume that integer operations issue and complete in 1 clock cycle (including loads) and that their results are fully bypassed. Ignore the branch delay. You will use the FP latencies (only), but assume that the FP unit is fully pipelined. For scoreboards below, assume that an instruction waiting for a result from another function unit can pass through read operands at the same time the result is written. Also assume that an instruction in WR completing will allow a currently active instruction that is waiting on the same functional unit to issue in the same clock cycle in which the first instruction completes WR.

Explanation / Answer

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