i have this function in vrilog: module fun1(x1,x2,x3,x5,x6,u); input x1,x2,x3,x5

ID: 3554111 • Letter: I

Question

i have this function in vrilog:

module fun1(x1,x2,x3,x5,x6,u);

input x1,x2,x3,x5,x6;

output [3:0]u;

wire b1,b2,b3,c1,c2,c3;

add2 bite0 (1,x5,0,b1,c1);

add2 bite1 (0,x6,c1,b2,b3);

add2 bite2 (x1,b1,0,u[0],c2);

add2 bite3 (x2,b2,c2,u[1],c3);

add2 bite4 (x3,b3,c3,u[2],u[3]);

endmodule

if x6 & x5 = 01 the ouput shuold be only function 1

f if x6 & x5 =10 the ouput shuold add function 1 + function 1

if x6 & x5 =11 the output shuold be function1+function1+function1

how to do that in vrilog?

input x1,x2,x3,x5,x6;

output [3:0]u;

wire b1,b2,b3,c1,c2,c3;

add2 bite0 (1,x5,0,b1,c1);

add2 bite1 (0,x6,c1,b2,b3);

add2 bite2 (x1,b1,0,u[0],c2);

add2 bite3 (x2,b2,c2,u[1],c3);

add2 bite4 (x3,b3,c3,u[2],u[3]);

endmodule

module call(x1,x2,x3,x5,x6,out);

input x1,x2,x3,x5,x6;

output [3:0]out; //out is the output that you want

wire [3:0] o;

fun1 f1(x1,x2,x3,x5,x6,o); //make a call to the function fun1 and store the result in wire o

case({x6,x5})

2'b01 : out=o1; //out=function1

2'b10 : out=o1+o1; //out=function1+function1

2'b11 : out=o1+o1+o1; //out=function1+function1+function1

endcase

endmodule

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