cache design (Cache Design) Suppose a 32-bit byte-addressable CPU accesses memor

Question

cache design

(Cache Design) Suppose a 32-bit byte-addressable CPU accesses memory in the following order: 17433, 17435, 17443, 17448, 17451, 17438, 17439, 17459. Assume that we have 4 cache blocks. Initially the cache is empty. (1 cache word = 4 bytes) If the cache is direct-mapped, show the final contents of the cache with memory block number. Assume 1 block is 1 word. (Ignore the tag field and other bits.) What is the total number of misses? If the cache is 2-way set associative with LRU replacement policy, show the final contents of the cache with memory block number. Assume 1 block is 2 words. (Ignore the tag field and other bits.) What is the total number of misses?

Explanation / Answer

a) cache has 1 block => 1 word i.e for first 17433 1 miss and it stores 17432 to 17435 so for second no miss for third 17443 we will have 17440 to 17443 1 miss again and for 17448 third miss 17451 will be thre in previous one so no miss for 17438 again fourth miss(this will include 17436 to 17439) 17439 no miss 17459 the fifth miss

b) least recently used so

17433 -> 1 miss 17432 to 17435

17435-> no miss

17443 -> 1 miss 17440 to 17443 17432 to 17435

17448 -> 1 miss 17448 to 17451 17440 to 17443

17451 -> no miss

17438 -> 1 miss 17436 to 17439 17448 to 17451

17439 -> no miss

17459 -> 1 miss 17456 to 17459 17436 to 17439

again 5 misses

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