The logic diagram below shows a 4-bit random sequence generator. Answer the foll
ID: 3558027 • Letter: T
Question
The logic diagram below shows a 4-bit random sequence generator. Answer the following questions to describe the functional behavior of the random sequence generator. Figure 1: 4-bit random sequence generator Suppose that the flip-flops are reset initially, list all states (Q3, Q2. Q1, Q0) in sequence. The timing characteristics of the components are summarized below. Flip-flop: clock-to-Q maximum delay tpcq = 40ps, clock-to-Q minimum delay tccq = 30ps, setup time tsetup = 50ps, hold time thold = 20ps Logic gate (each AND, OR, Inverter, XNOR): propagation delay tpd = 35ps, contamination delay tcd = 15ps. Derive the minimum clock period. Draw the timing diagram of Q3 for the first 6 clock cycles.Explanation / Answer
3.1) IF all flip flops are reset initially, we have the following states = Q3=Q==Q1=Q0 =0
3.2) Minimum Clock Period =
Using the formula of Tmin = max(Tpcq) + (n-2)max(Tpd) + Tcd + Tsu + Thold
= 40 +2*35 + 15 + 50 +20 = 195
3.3) Timing Diagram of Q3 for first 6 clock cycles =
first cycle = Q3 = 0
Second Cycle Q3 = 1
Third Cycle = 0
fourth cycle = Q3 = 1
Fifth Cycle Q3 = 0
Sixth Cycle = 1
Now draw a diagram on basis of these values
_|1|_|1|_|1|
replace 1 by one upward upperscore
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