5.2 Caches are important to providing a high-performance memory hierarchy to pro

Question

5.2 Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses.

3, 180, 43, 2, 191, 88, 190, 14, 181, 44, 186, 253

5.2.3 You are asked to optimize a cache design for the given references. There are three direct-mapped cache designs possible, all with a total of 8 words of data: C1 has 1-word blocks, C2 has 2-word blocks, and C3 has 4-word blocks. In terms of miss rate, which cache design is the best? If the miss stall time is 25 cycles, and C1 has an access time of 2 cycles, C2 takes 3 cycles, and C3 takes 5 cycles, which is the best cache design?

Explanation / Answer

From the given data, Direct-Mapped cache with 8words of data means 2^3 of data.

There are three caches C1, C2 and C3.
C1 has 1 word blocks
C2 has 2 word blocks
C3 has 4 word blocks
also, Miss stall = 25 cycles.
We have,
Miss rate = 3% for current block size
Thus, for cache C1, miss rate = 3%
cache C2, miss rate = 2%
cache C3, miss rate = 1.2%
So, the cache C3 design is the best. In terms of miss rate. The cache performance increases with decrease in miss penalty.
That means if miss penalty is less, then the performance of cache increases. And for cache C3, the miss penalty is less.

From given data
C1 acess time is 2 Cycles.
C2 acess time is 3 Cycles.
C3 acess time is 5 Cycles.
Then
C1 stall time is 25*11+ 2*12 = 299.
C2 stall time is 25*9+ 3*12 = 261.
C3 stall time is 25*10+ 5*12 = 310.
In this case, C2 is the best cache design.
And
C1 stall time is 25*11+ 2*12 = 299.
C2 stall time is 25*8+ 3*12 = 236.
C3 stall time is 25*8+ 5*12 = 260.
In this case also, C2 is the best cache design.

Please rate me. Thanks a lot.

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