5.6 In this exercise, we will look at the different ways capacity affects overal
ID: 3568938 • Letter: 5
Question
5.6 In this exercise, we will look at the different ways capacity affects overall performance. In general, cache access time is proportional to capacity. Assume that main memory accesses take 70 ns and that memory accesses are 36% of all instructions. The following table shows data for L1 caches attached to each of two processors, PI and P2. Assuming that the L1 hit time determines the cycle times for P1 and P2, what are their respective clock rates?> What is the Average Memory Access Time for P1 and P2? > Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for PI and P2? Which processor is faster? For the next three problems, we will consider the addition of an L2 cache to P1 to presumably make up for its limited L1 cache capacity. Use the LI cache capacities and hit times from the previous table when solving these problems. The L2 miss rate indicated is its local miss rate. What is the AMAT for P1 with the addition of an L2 cache? Is the AMAT better or worse with the L2 cache? Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 with the addition of an L2 cache? Which processor is faster, now that PI has an L2 cache? If P1 is faster, what miss rate would P2 need in its LI cache to match P I's performance? If P2 is faster, what miss rate would PI need in its LI cache to match P2's performance?Explanation / Answer
5.6.1
Respective clock rates = 1/L1 hit time
a) Clock Rate for P1 Processor = 1/ 0.66 = 1.515 GHz
b) Clock Rate for P2 Processor = 1/0.9 = 1.11 GHz
5.6.2.
a) Average Memory Access Time For P1 = L1 hit time + (L1 miss rate * Memory Access Time)
=> (AMAT FOR P1) = 0.66 + (8%*70) = 0.66 + 5.6 = 6.26 ns
b) Average Memory Access Time For P2 = L1 hit time + (L1 miss rate * Memory Access Time)
=> (AMAT FOR P1) = 0.90 + (6%*70) = 0.90 + 4.2 = 5.1 ns
5.6.3
a) Total CPI For P1 = Base CPI + [(Memory Access Time*L1 miss rate)/L1 Hit time] * Number of memory instructions
=> Total CPI For P1 = 1 + [(70*8%)/0.66]*0.36 = 4.054
b) Total CPI For P2 = Base CPI + [(Memory Access Time*L1 miss rate)/L1 Hit time] * Number of memory instructions
=> Total CPI For P2 = 1 + [(70*6%)/0.90]*0.36 = 2.68
As Total CPI For P2 is less than the Total CPI For P1, Processor P2 is Faster.
5.6.4
Average Memory Access Time For P1 with the addition of a L2 Cache
= L1 hit time + L1 Miss rate*(L2 Hit time + L2 Miss rate*Memory Access Time)
= 0.66 + 8%*(5.62+95%*70)
= 0.66 + 8%*(5.62+66.5)
= 0.66 + 8%*72.12 = 0.66 + 5.76 = 6.4296 ns
As the average memory access time has increased now, the AMAT has become worse on adding an extra L2 Cache.
5.6.5
Total CPI = Base CPI + Number of memory instructions * [L1 miss rate * ( L2 Hit in Cycles + L2 Memory Miss In Cycles)]
= 1 + 0.36*[0.08*(5.62+0.95*70)/0.66] = 1 + 0.36*[0.08*109.27] = 4.14
5.6.6
Now processor P2 is only faster though P1 has a L2 Cache.
P2 time = 2.68*0.9 = 2.41 ns/instruction
For P1 to be faster than P2, 0.66 * (1+0.36*X*106) < 2.41
Solve to get X which is:-
X = 0.069 = 69% Miss Rate
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