Consider the following assembly language code: add $R3.$R1.$R0://ADD R3 = RI + R

Question

Consider the following assembly language code: add $R3.$R1.$R0://ADD R3 = RI + R0 Iw $R2, 100($R3)://LDW R2 - MEM[R3 + 100] sub $R9, $R3, $R2://SUB R9 = R3 - R2 udd $R4, = $R5, $R6://ADD R4 = R5 + R6 sw 100($R4), $R2;//STW M1:M[R4 + 100] = R2 addi $R2, $R1, 12://ADDI R2 = R1 + 12: beq $R7, $R 1, Label;//BEQ R7 = R1, Label; Iw $R7, 120($R 1);//LDW R7 = MEM[R1 + 120); Consider a pipeline with forwarding, hazard detection, and I delay slot for branches. The pipeline is the typical 5-stage IF, ID, EX, MEM, WB MIPS design. For the above code, complete the pipeline diagram below (instructions on the left, cycles on top) for the code. Insert the characters IF, ID, EX, MEM, WB for each instruction in the boxes. Assume that there two levels of bypassing, that the second half of the decode stage performs a read of source registers, and that the first half of the write-back stage writes to the register file. Label all data stalls (Draw an X in the box). Label all data forwards that the forwarding unit detects (arrow between the stages handing off the data and the stages receiving the data). (a) What is the final execution time of the code?

Explanation / Answer

In the above pipeline diagram, we could see that instruction starts at 0th cycle and ends at 12th cycle. Pipeline diagram is already correct. Hence, it would take 12 cycles to execute the 7 instructions given above.

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