(Processor Architecture) One way of dealing with branch instructions is to use t
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(Processor Architecture) One way of dealing with branch instructions is to use the concept of predicated instruction.
N1. One way of dealing with branch instructions is to use the concept of predicated instruction. For example, each instruction is tagged with 1-bit condition, and then processor executes the instruction only if the condition tag is l (true). Consider a predicated instruction with a pair of 1-bit predicate registers pT and pF: (pT) ADD RO, RO, R4 which RO RO+R4 if (pT) 1. i.e. True. Otherwise, the ADD instruction behaves as would a NOP instruction Let's assume there's a new instruction setting the predicate registers: CMP EQ pT, pF-R1, R2 which means 1-bit value of the predicate registers pT and pF will be assigned as a result of comparing R1 and R2 to pT (R1 R2) and pF (R1 R2). For the code structure shown below, answer the questions: L1 if then L2 else 1...... L3 L4Explanation / Answer
Atleast two predicate registers are needed. One register for outer if-else branch and atleast one register for inner conditional branch of 'then' clause.
(We need atleast one for inner branch in case the condition is simple if-else and need more for complex branching.)
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