Computer Architecture MIPS cache and hit/miss rate Assume an instruction cache m

Question

Computer Architecture MIPS cache and hit/miss rate

Assume an instruction cache miss rate for an application is 2% and the data cache miss rate of 4%. Assume further that our CPU has a CPI of 2 without any memory stalls and the miss penalty is 40 cycles for all misses. Determine the overall CPI with the indicated misses, provided the frequency of all loads and stores in the application is 20%. Suppose we increase the performance of the machine in the above example by reducing its CPI from 2 to 1 via pipelining. Determine the new overall CPI.

Explanation / Answer

(a)

Instruction miss cycles=I*2%*40=0.80I

Data Miss Cycles=I*20%*4%*40=I*(20/100)*(4/100)*40=0.32I

The CPI with Memory stalls is : 2+0.80+0.32=3.12

(CPU stall)/(CPU perfect)=(I*CPI stall*clock cycles)/(I*cpi perfect*clock cycles)
=>3.12/2
=>1.56

(b)

Repeat the problem with CPI=1
The CPI considering memory stalls is 1+0.80+0.32=2.12
(CPI stall)/(CPI perfect) = 2.12/1=2.12, we are loosing performance!

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