Complete the state transition diagram for the following write-invalidate snoopy
ID: 3575508 • Letter: C
Question
Complete the state transition diagram for the following write-invalidate snoopy protocol for cache coherence control. Assume that non-write-allocate policy is applied at the Invalid state. All transition edges must be properly labeled with local cache events (R, R/F, or W) or snoopy bus events (BR or BW). Listed below are 5 possible cache or bus events and their notations.
R: A local processor reads a local cache block.
R/F: From the invalid state, a local processor reads a cache block from the main memory. W: A local processor writes into a local cache block
BR: A remote processor reads its own cache block with the same address.
BW: A remote processor writes its own cache block with the same address.
At the modified state, the write back is always enforced after an external read or an external write is monitored on the snoopy bus. Similarly, write back must follow the local write from a shared state. No write back is enforced in all other transitions. Please note the difference between Exclusive (writeable, clean) and Modified (written, dirty) states. What are the pros/cons of this protocol comparing to the three-state snoopy-bus protocol that we discussed in class?
Shared R only Invalid BW Exclusive Modified R only R/W WExplanation / Answer
Answer:
CPU wanting to write to an address, grabs a bus cycle and sends a ‘write invalidate’ message All snooping caches invalidate their copy of appropriate cache line CPU writes to its cached copy. Any shared read in other CPUs will now miss in cache and re-fetch new data.Snooping Protocols • Write Update CPU wanting to write grabs bus cycle and broadcasts new data as it updates its own copy All snooping caches update their copy • Note that in both schemes, problem of simultaneous writes is taken care of by bus arbitration - only one CPU can use the bus at any one time.
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