Briefly answer the following questions. What are the impacts of converting a har

Question

Briefly answer the following questions. What are the impacts of converting a hardware component into a pipelined version in terms of its latency and throughput? List a code segment that contains two MIPS instructions for which the data forwarding technique can completely remove the pipeline stall associated with the hazard. For the MIPS five-stage instruction pipe, do the three register numbers for the instruction (add $sl, $s2, $s3) reach the input side of the register file at the same time? If yes, why? If no, why not? What is the main benefit of using the loop unrolling technique on a superscalar processor?

Explanation / Answer

Latency:
Latency is the time to complete a single instruction from start to finish.

Throughput:
Throughput is the maximum rate at which instruction can be processed

Pipeline:
Pipeline is a set of data processing instructions connected in series,
where the output of one instruction is the input of the next one.
The instructions of a pipeline are often executed in parallel or
in time-sliced fashion;

Pipeline impact on Throughput and Latency:
Pipelining increases instruction throughput by performing multiple operations at the same time,
but does not reduce instruction latency

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