Problem 4: Multiprocessor Cache Coherence (13 points) Assume a 2 processor share

Question

Problem 4: Multiprocessor Cache Coherence (13 points) Assume a 2 processor shared memory system with private cache in each processor, and a snooping bus cache coherence protocol using write invalidate. Now consider the following sequence of operations from two processors, labeled P1 and P2, to shared data.(Assume initial values in memory A-20 and 8-10 and assume they map to different cache blocks.) P1: Read A P2: Read A P1: Write A-40 P2: Read A P2: Read Bs P2: Write B-50 P1: Read A Describe the sequence of events generated (on bus and processor) the actions taken, and the state of the cache and memory during the execution of the above code. (You should explain events at each step/cycle; you can explain it using a figure/table similar to the case study from the text, or write out sentences that describe the behavior.)

Explanation / Answer

P1: Read A

- P1 will take control of A and B to overcome from deadlock.

- P1 initiates a read bus cycle by floating the address of the memory location on the address lines.

- Once the address lines are stable, the processor asserts the address strobe signal on the bus. The address strobe signals the validity of the address lines.

- P1 sets the Read signal to high.

Now the P1 asserts the data strobe signal. This signals to the memory that the processor is ready to read data.

-The memory subsystem decodes the address and places the data on the data lines.The memory subsystem then asserts the data acknowledge signal. This signals to the P1 that valid data can now be latched in.

-P1 latches in the data and negates the data strobe. This signals to the memory that the data has been latched by the processor.P1 also negates the address strobe signal.Memory subsystem now negates the data acknowledgement signal. This signals the end of the read bus cycle.

P2:Read A

- P2 will take control of A and B to overcome from deadlock.

- P2 initiates a read bus cycle by floating the address of the memory location on the address lines.

- Once the address lines are stable, the processor asserts the address strobe signal on the bus. The address strobe signals the validity of the address lines.

- P2 sets the Read signal to high.

Now the P2 asserts the data strobe signal. This signals to the memory that the processor is ready to read data.

-The memory subsystem decodes the address and places the data on the data lines.The memory subsystem then asserts the data acknowledge signal. This signals to the P2 that valid data can now be latched in.

-P2 latches in the data and negates the data strobe. This signals to the memory that the data has been latched by the processor.P2 also negates the address strobe signal.Memory subsystem now negates the data acknowledgement signal. This signals the end of the read bus cycle.

P1: Write A=40
-P1 initiates a write bus cycle by floating the address of the memory location on the address lines.
-Once the address lines are stable, the P1 asserts the address strobe signal on the bus. The address strobe signals the validity of the address lines.
-P1 then sets the Read/Write* signal to low, i.e. write.
-The P1 then places the data on the data lines.
-Now the P1 asserts the data strobe signal. This signals to the memory that the P1 has valid data for the memory write operation.
-The memory subsystem decodes the address and writes the data into the addressed memory location.
-The memory subsystem then asserts the data acknowledge signal. This signals to the P1 that data has been written to the memory.
-Then the P1 negates the data strobe, signaling that the data is no longer valid.
-P1 also negates the address strobe signal.
-Memory subsystem now negates the data acknowledgement signal, signaling an end to the write bus cycle.

-Finally A will have 40.

P2 :Read A

- By same procedure P2 will go to A location and read A.

P2:Read B

-By same procedure define for reading P2 will read B value.

P2: Write B=50

-P2 initiates a write bus cycle by floating the address of the memory location on the address lines.
-Once the address lines are stable, the P2 asserts the address strobe signal on the bus. The address strobe signals the validity of the address lines.
-P2 then sets the Read/Write* signal to low, i.e. write.
-The P2 then places the data on the data lines.
-Now the P2 asserts the data strobe signal. This signals to the memory that the P2 has valid data for the memory write operation.
-The memory subsystem decodes the address and writes the data into the addressed memory location.
-The memory subsystem then asserts the data acknowledge signal. This signals to the P2 that data has been written to the memory.
-Then the P2 negates the data strobe, signaling that the data is no longer valid.
-P2 also negates the address strobe signal.
-Memory subsystem now negates the data acknowledgement signal, signaling an end to the write bus cycle.

-Finally 50 will go into B.

P1: Read A

- By same procedure define for reading P1 will read A.

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