Problems: 1. How long will the following code fragment take to issue on an in-or

Question

Problems: 1. How long will the following code fragment take to issue on an in-order superscalar processor with three execution units, where all instructions have latencies of 1 cycle and any execution unit can execute any instruction? LD , (r2) SUB r4, r5, r6 ADD r3, rl, r7 MUL r8, r3, r3 ST (r1), r4 ST (r12), r8 ADD rl5, r14, r13 SUB r10, rl5, r10 DIV r, r7, r3 SUB r3, r4, r8 OR r10,r7, r0 ASH r2, r14, r6 2. What is the longest chain of dependent operations (including name dependencies) in the code provided in problem 1? 3. How long the code fragment from problem 1 take to issue on an out-of-order superscalar processor with all other parameters the same as problem 1? Assume the instruction window of the processor is large enough to cover the entire code fragment and that the processor takes the greedy approach to issuing instructions. 4. What are the advantages and disadvantages of using VLIW processors in ILP?

Explanation / Answer

How long will the following code fragment take to issue on an in-order superscalar processor with three execution unit, where
all instructions have latencies of 1 cycle and any execution unit can execute any instruction?

Answer : Thiscode fragment takes 6 cycles to issue . Note that there are severalinstructionsin the fragment whose data depnendecies
would allow them to be executed earlier, but that the processor cannot move up any earlier because of the in-order
execution requirement.
Cycle 1 :LD r1,(r2)
Cycle 2 :ADD r3,r1,r7
Cycle 3 :MUL r8,r3,r3
Cycle 4 :ST (r12)r8
Cycle 5 :SUB r10,r15,r10
Cycle 6 :ST(r9),r10

2.The longest chain of dependencies is four instructions long
LD r1,(2)
MUL r8,r3,r3
ST (r12),r8
ADD r15,r14,r13
Note that the dependency between the ST and the ADD instructions is a WAR dependency

3. It would take 5 cycles.
Cycle 1: LD r1,(r2)
Cycle 2: ADD r3,r1,r7
Cycle 3: MUL r8,r3,r3
Cycle 4: ST(r12),r8
Cycle 5: r9,(r10)

4. Very long instruction word (VLIW) refers to instruction set architectures designed to exploit instruction level parallelism (ILP).
Very large instruction word means that program recompiled in the instruction to run sequentially without the stall in the pipeline
Each instruction specifies several independent operations (called very long words) that are executed in parallel by the hardware
Advantages
**********
=> Reduces hardware complexity
=> Ensure potentially higher clock rate.
=> Ensures low power consumption.
=> Simpler instruction-issue logic in them.
=> Their simpler instruction issue logic also often allows VLIW processors to fit more execution units onto a given amount of chip space than
superscalar processors
Disadvantages
*************
=> Higher complexity of the compiler
=> Code exansion :causes high power consumption.
=> Unscheduled events(eg. cache miss)stall entire processor.
=> Changing instruction latencies between generations of a processor family can cause operations to execute before their inputs are
ready or after their inputs have been overwritten, resulting in incorrect behavior
=> If the compiler cannot find enough parallel operations to fill all of the slots in an
instruction, it must place explicit NOP (nooperation) operations into the corresponding operation slots

Related Questions

Navigate

• Browse (All)
• Browse P
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.