For this laboratory assigment, you\'ll use Altera Quartus Il software abd DE2-11

Question

For this laboratory assigment, you'll use Altera Quartus Il software abd DE2-115 FPGA kit and design a BCD incrementor that has the Input/output definitions below. BCD BCD BCD Number [7:0 INCREMENTOR Output [7:0) INCREMENTOR Ti T TIL TTLLL I IIUL The Binary-Coded-Decimal (BCD) format uses 4 bits to represent 10 decimal digits. For example (64)1o is represented as "0110 1000" in BCD format. A BCD incrementor adds 1 to a number in BCD format, so after incrementing our number becomes (64)o and "0110 1000". INPUT and OUTPUT has 8 bits which represents 2 digits. Design a 2-digit incrementor and derive the FPGA Code. Take the input from 8 switches that you designated. Show the output on Seven-Segment of the FPGA. Increment it again then show the output on the Seven Segment which connected to GPIO pins of your FPGA DON'T FORGET THE RESISTORS BETWEEN GPIO AND SEVEN SEGMENT. IF YOU DON'T CONNECT, THE GPIO LEG CAN BURN.

Explanation / Answer

According to the question I would try to drive each segment atleat 50% of the time. Please find the code below: module PartD( input clock, input reset, output reg[0:6] lcd, //for one particular 7 segment LCD. output reg[7:0] sel // for selecting which LCD to be used ); reg [26:0]count; reg[3:0] i, j; //4 bit reg for counting always@(posedge clock) begin count

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