using VHDL for the Altera DE-270 FPGA: Implement an 8 bit counter that resets to
ID: 3600202 • Letter: U
Question
using VHDL for the Altera DE-270 FPGA: Implement an 8 bit counter that resets to zero when pushbutton KEY3 is pressed and counts up by one each time pushbutton KEY2 is pressed. Pushbuttons are active low (i.e. normally high) and are debounced in hardware. The value in the counter should be displayed in the two leftmost seven-segment LEDs (HEX7 (HEX7_D[*]) and HEX6 (HEX6_D[*])) as
a hexadecimal number. Note that the LED segments are active low (i.e., the segment is illuminated when the corresponding I/O pin is driven low). Your counter should be designed from basic gates -- that is, do not simply use VHDL's ability to add one to an integer as a way to build a counter. For this problem set, start by implementing a full-adder
component. Use the full-adder to implement an 8-bit adder component. Implement a component that converts a four-bit vector into a vector for a seven-segment display. Implement an 8-bit register with clear capability. Use instantiations of these components to build your top-level entity.
Explanation / Answer
ing VHDL for the Altera DE-270 FPGA: Implement an 8 bit counter that resets to zero when pushbutton KEY3 is pressed and counts up by one each time pushbutton KEY2 is pressed. Pushbuttons are active low (i.e. normally high) and are debounced in hardware. The value in the counter should be displayed in the two leftmost seven-segment LEDs (HEX7 (HEX7_D[*]) and HEX6 (HEX6_D[*])) as
a hexadecimal number. Note that the LED segments are active low (i.e., the segment is illuminated when the corresponding I/O pin is driven low). Your counter should be designed from basic gates -- that is, do not simply use VHDL's ability to add one to
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