Problem 7 (10 points): Write an 8:1 multiplexer module in Verilog, called mux8 w

Question

Problem 7 (10 points): Write an 8:1 multiplexer module in Verilog, called mux8 with selection input s[2:0], data inputs do, d1, d2, d3, d4, d5, d6, d7, and data output y. The bit width of all data inputs and outputs should be parameterized by "width". Use "case" statement with behavioural model. Problem 8 (10 points): Write a structural module in Verilog to compute the logic function, y = ab' + b,c, + abc, using multiplexer logic. Use the 8:1 multiplexer from Problem 7 as the building block with structural model only

Explanation / Answer

problem 7

module mux8to1(d,s,y)

input [0:7]d;

input [2:0]s;

output y;

reg y;

always @(d or s)

case (s[2:0])

0:output d[0];

1:output d[1];

2:output d[2];

3:output d[3];

4:output d[4];

5:output d[5];

6:output d[6];

7:output d[7];

end case

end module

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