Problems in this exercise refer to the following sequence of instructions, and a

Question

Problems in this exercise refer to the following sequence of instructions, and assume that it is executed on a five-stage pipelined datapath:

ADD X5, X2, X1

LDUR X3, [X5, #4]

LDUR X2, [X2, #0]

ORR X3, X5, X3

STUR X3, [X5, #0]

a). If there is no forwarding or hazard detection, insert NOPs to ensure correct execution.

b). Now, change and/or rearrange the code to minimize the number of NOPs needed. You can assume register X7 can be used to hold temporary values in your modified code.

c). If there is forwarding, for the first seven cycles during the execution of this code, specify which signals are asserted in each cycle by hazard detection and forwarding units in Figure 4.59.

Figure 4.59:

Hazard detection unit ID/EX.MemRead ID/EX WB EX/MEM Control WB MEM/WB IF/ID WB Registers ForwardA ALU Instruction memory Data memory ForwardB IF/ID.RegisterRn IF/ID.RegisterRm IF/ID.RegisterRd Rd Rn Rm Forwarding unit FIGURE 4.59 Pipelined control overview, showing the two multiplexors for forwarding, the hazard detection unit, and the forwarding unit. Although the ID and EX stages have been simplified-the sign-extended immediate and branch logic are missing this drawing gives the essence of the forwarding hardware requirements.

Explanation / Answer

when we compared the single cycle cpu to the multiple cycle cpu, we saw a decrease in cycle time, and an increase in cpi. with a pipelined processor, we get the best of both: the low cpi of the single cycle cpu, and the low cycle time of the multiple cycle cpu. the cost, as usual, is increased complexity.

note that pipelining does not improve the performance of a single instruction. rather, it improves the performance of groups of instructions. this is one of the classic issues in computer science: latency vs. throughput. a pipelined processor can't execute a single load instruction any faster than a multi-cycle cpu. however, a pipelined processor can execute five load instructions faster than a multi-cycle cpu.

pipelined datapath

as you look over the pipelined datapath, you should notice that it looks like a weird combination of the single and multiple cycle cpus. like the single cycle cpu, we have extra adders to compute pc+4 and the branch target. we also have separate instruction and data memories. on the other hand, we have lots of extra registers, like the multiple cycle cpu.

you'll also notice that the pipeline registers are placed in familiar locations, from our multicycle cpu. the if/id register is placed where the ir [instruction register] register was, the id/ex register is placed where a and b were, the ex/mem register is placed where aluout was, and the mem/wb register is placed where mdr [memory data register] was. this results in the same five stages that we know so well from our multi cycle cpu: fetch, decode, execute, memory, writeback.

unlike the multi cycle cpu, the pipelined datapath requires that every instruction use all five stages of execution. why? because we end up with resource conflicts if instructions with different latencies are run in parallel.

suppose we use the latencies from our multi-cycle cpu, and we try to run a load instruction followed by an add instruction. the load instruction will require five cycles to execute, and the add instruction will require four cycles. so, if we start running the load instruction on cycle 1, it will finish execution on cycle 5. we are pipelining, so we can start running the add instruction on cycle 2, and it will finish on cycle 5. this is a problem: we have two instructions finishing on cycle 5: they will both try to write to the register file on cycle 5. this is a problem, because our register file only has one write port.

we eliminate these types of resource conflicts by requiring every instruction to go through all five cycles of execution.

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