Consider adding a new addressing mode to MIPS. The addressingmode adds the conte

Question

Consider adding a new addressing mode to MIPS. The addressingmode adds the contents of
two registers with an 10-bit signed offset to obtain the effectiveaddress.
Our compiler will be changed so that code sequences of the form

ADD, R1, R1, R2
LW Rd, 100(R1) (or store)
will be replaced with a load (or store) using the new addressingmode. Studies on overall
instruction frequencies show that 35% of instructions are loads andstores.
a. Assume that the addressing mode can be used for 15% of thedisplacement loads and
stores. What is the ratio of instruction count on the enhanced MIPScompared to the
original MIPS?
b. If the new addressing mode lengthens the clock cycle by 7%,which machine will be
faster and by how much? Consider adding a new addressing mode to MIPS. The addressingmode adds the contents of
two registers with an 10-bit signed offset to obtain the effectiveaddress.
Our compiler will be changed so that code sequences of the form

ADD, R1, R1, R2
LW Rd, 100(R1) (or store)
will be replaced with a load (or store) using the new addressingmode. Studies on overall
instruction frequencies show that 35% of instructions are loads andstores.
a. Assume that the addressing mode can be used for 15% of thedisplacement loads and
stores. What is the ratio of instruction count on the enhanced MIPScompared to the
original MIPS?
b. If the new addressing mode lengthens the clock cycle by 7%,which machine will be
faster and by how much?

Explanation / Answer

Dear... a)     Load+Store=0.26+0.15=0.41        15% of 0.41instructions are eliminated          End ofinstructions =1-0.15*0.41                                    =1-0.0615                                     =0.9385 b)    Time oiginal=1         Time enhanced=0.9385*1.07                                =1.004     The enhanced version is 1% slower. Hope this willl help you...

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