Assignment No. 02 Semester Spring 2009 Advance Computer Architectuer-CS501 Total

Question

Assignment No. 02
Semester Spring 2009
Advance Computer Architectuer-CS501

Total Marks: 25

Due Date: 14/04/2009

Objective:
To learn and understand basic concepts of Logic Design and ControlSignals Generation in SRC.

Instructions:
Please read the following instructions carefully before solving& submitting assignment:
Assignment should be in your own wordings not copied from net,handouts or books.
It should be clear that your assignment will not get any credit(zero marks) if:

o The assignment is submitted after due date.
o The submitted assignment does not open or file corrupt.
o The assignment is copied (from other student or copy fromhandouts or internet).
o Student ID is not mentioned in the assignment File or nameof file is other than student ID.

For any query about the assignment, contact at cs501@vu.edu.pk

GOOD LUCK
  

(a) What will be the logic levels on the external SRC buses wheneach of the given SRC instruction is
executing on the processor? Complete Table:A all numbers arein the decimal number system, unless
noted otherwise. (Assume the required missing information ifnecessary)          

(b) Specify memory addressing modes for each of the SRCinstructions given in Table.


SRC
instruction
RTL Equivalent Address
Bus<31….0>
Data Bus
<31….0>
MRead MWrite
Ld
r3,12(r5)
    
Ldr2,16          
Table: A


Assumptions:

• All memory content is aligned properly.
• In other words, all the memory accesses start ataddresses divisible by 4.  
• Value in the PC = 000DC348h






Memory map with assumed values




Register map with assumed values

Explanation / Answer

Solution:-Part 1:-

SRC Instruction

RTL Equilent

Address bus <31 0>

Data bus

<31   0>

M(R)

M(W)

LD r3,12(r5)

R[3]<-M[12+R[5]

00AB1240h

0785E530h

1

LD r2,16

R[2]<-M[16]

00000020h

D296492fh

1

Part2:-

Solution:-

Memory Addressing

SRC Instruction

LD r7,12(r5)

LD r2,16

Addressing Mode

Displacement

Direct

SRC Instruction

RTL Equilent

Address bus <31 0>

Data bus

<31   0>

M(R)

M(W)

LD r3,12(r5)

R[3]<-M[12+R[5]

00AB1240h

0785E530h

1

LD r2,16

R[2]<-M[16]

00000020h

D296492fh

1

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