In this exercise, we will explore the control unit for a cache controller for a

Question

In this exercise, we will explore the control unit for a cache controller for a processor with a write buffer. Use the finite-state machine found in Figure 5.34 as a starting point for designing your own finite-state machines. Assume that the cache controller is for the simple direct-mapped cache described on page 530, but you will add a write buffer with a capacity of one block. Recall that the purpose of a write buffer is to serve as temporary storage so that the processor doesn't have to wait for two memory accesses on a dirty miss. Rather than writing back the dirty block before reading the new block, it buffers the dirty block and immediately begins reading the new block. The dirty block can then be written to main memory while the processor is working. What should happen if the processor issues a request that hits in the cache while a block is being written back to main memory from the write buffer? What should happen if the processor issues a request that misses in the cache while a block is being written back to main memory from the write buffer? Design a finite-state machine to enable the use of a write buffer.

Explanation / Answer

please rate - thanks 5.15.1 The cache should be able to satisfy the request since it isotherwise idle when the write buffer is writing back to memory. If the cache isnot able to satisfy hits while writing back from the write buffer, the cache willperform little or no better than the cache without the write buffer, since requests willstill be serialized behind writebacks. 5.15.2 Unfortunately, the cache will have to wait until thewriteback is complete since the memory channel is occupied. Once the memory channel isfree, the cache is able to issue the read request to satisfy the miss. 5.15.3 Correct solutions should exhibit the following features: 1. The memory read should come before memory writes. 2. The cache should signal “Ready” to the processorbefore completing the write. Example (simpler solutions exist, the state machine is somewhatunderspecifi ed in the chapter): sorry your on your own for the machine

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