3. Consider a non-pipelined machine with 6 execution stages, each on with a leng

Question

3. Consider a non-pipelined machine with 6 execution stages, each on with a lengthof 50 ns. (a) Find the instruction latency (the execution time of each instruction) on this machine. (b) How much time does it take to execute 100 instructions?
4. Suppose we introduce pipelining on the machine mentioned in Q3. (a) What is the instruction latency on the pipelined machine? (b) How much time does it take to execute 100 instructions? Calculate the actual time. Assume that there is no overhead.
5. (5 points) Discuss at least two problems with pipelining.
6. (5 points) What is a superscalar computer?

Explanation / Answer

question 3 )
a) since each stage is of 50ns.so execution of 6 stage will take :
50ns * 6 = 300ns
execution of 6 stages = execution of each instruction = 300ns
b) time taken in execution of 1 instruction = 300ns.
time taken in execution of 100 instruction = 300 * 100 = 30ms.

question 4)
since by introduction of pipeline the running time of each instruction does not change ,only throughput increases.
so execution time for one instruction = 6* 50 = 300ns
total time taken in pipelined system for 100 instruction = ( k + n - 1) * time taken in execution of one stage
where k = number of stages in pipeline
n = number of instruction
so total time = ( 6 + 100 - 1) * 50
= 5250 ns
= 5.25 ms
speed up of pipelined processor = 30 /5.25 = 5.714

question 5)
problems due to pipelining are called pipelining hazards,
they are of three types.
a) data hazards :
Since pipelining overlaps the execution of instructions ,so there may be possible that next instruction uses output of current instruction as the input . the output of current instruction will not be available till register write stage and we fetch the operands for next instruction before the register write phase of current instruction is complete .this stalls the pipeline and pipeline stops until the register write stage completes successfully .
example : in mips assembly language :
ADD $1 $2 $3 #addition of register 2 and 3 and the output is stored in register 1
SUB $4 $5 $1 #reg(5) - reg(1) = reg(4)
b) structural hazards .
They arise from resource conflicts when the hardware cannot support all possible combinations of instructions in simultaneous overlapped execution.If some combination of instructions cannot be accommodated because of a resource conflict, the machine is said to have a structural hazard.
example : a machine may have only one register-file write port, but in some cases the pipeline might want to perform two writes in a clock cycle.
c) control hazards : occurs due to branch instructions which changes the content of PC ,thus changing the normal flow of execution.

question 6)
SuperScalar Processor :
A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor.
A superscalar processor executes more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to redundant functional units on the processor.
some properties of SuperScalar Processor :
1) Instructions are issued from a sequential instruction stream
2) CPU hardware dynamically checks for data dependencies between instructions at run time.
3) The CPU accepts multiple instructions per clock cycle
They can be Categorized into two categories.
1) SISD(single instruction single data stream)
2) MIMD ( multiple instruction multiple data stream)
3) SIMD ( single instruction multiple data stream)

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