Consider two processors with different cache configurations: Cache 1: Direct-map

Question

Consider two processors with different cache configurations: Cache 1:
Direct-mapped with one-word blocks
Cache 2: Two-way set associative with four-word blocks
The following miss rate measurements have been made:
Cache 1: Instruction miss rate is 3%; data miss rate is 6% Cache 2:
Instruction miss rate is 2%; data miss rate is 3%

For these processors, one-half of the instructions contain a data
reference. Assume that the cache miss penalty is 6 + Block size in
words. Determine which processor spends more cycles on cache misses

Explanation / Answer

For Cache 1: Miss penalty = 6 + 1 = 7 cycles Stall cycles per instruction = 3% × 7 + 50% × 6% × 7 = 0.21 + 0.21 = 0.42 For Cache 2: Miss penalty = 6 + 4 = 10 cycles Stall cycles per instruction = 2% × 10 + 50% × 3% × 10 = 0.2 + 0.15 = 0.35 hence Cache 1 spends more cycles

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