In this question, we examine the impact of DRAM scaling in current multicore pro

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In this question, we examine the impact of DRAM scaling in current multicore processors. Typically, a processor will have one or more DRAM controllers that process requests to external DRAMs, over a set of pins. Typically, the # of pins available does not change with each process generation, but the frequency that we can drive those pins at does, since the transistors that drive them get faster with each process generation. As a result, as we have gone from one generation of DRAM (e.g. DDR2) to the next (e.g. DDR3), we see the frequency of signaling over the pins increase approximately as the same speed that native transistor speeds increase. Note however that the capacitance of the pins does not scale with process generation. Assume that we are in a Leakage-Limited scaling regime, and that power budgets remain constant. Assume also that we are looking at scaling over two process generations (i.e., that S =2). You should show the symbolic derivation of any quantities as well as the final numerical value with S = 2 plugged in. FOR PARTIAL CREDIT SHOW YOUR WORK. DENNARDIAN BREAKDOWN Assuming that we keep the same clock frequency when we scale down, how much more energy efficient will a scaled core be? (Disregard any effects due to pins, DRAM etc.) Let's suppose that Intel decides to take advantage of Moore's Law via increasing the # of cores as opposed to increasing the frequency of their designs. By what factor will the # of cores increase when the process is scaled? Let's assume that the benchmark suite being targeted consists of HPC (high performance computing) applications that access large arrays sequentially in a highly predictable manner. These arrays

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here is solution manual http://www.docstoc.com/docs/15103657/Solution-manual-for-Computer-Architecture---4th-Ed-by-Patterson

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