Write the Verilog code and test bench for a full adder using AND, ORS, and NOTs

Question

Write the Verilog code and test bench for a full adder using AND, ORS, and NOTs only. Name your design module Fulladder and your test bench Fulladder_TB. you must show the complete code for both the design module and the test bench modle. Calculate the outputs and test your circuit with: b. A = 1, B = 0, Cin 1 =, Cout = ?, S = ? b. A = 1, B = 0, Cin 1 =, Cout = ?, S = ? b. A = 1, B = 0, Cin 1 =, Cout = ?, S = ? b. A = 1, B = 0, Cin 1 =, Cout = ?, S = ? Create a waveform(you do not have to simulate it, just predict it) of your inputs and outputs assuming a 30 ns delay for the AND gate, 20 ns for the OR gate and 10 ns for the NOT gate. Make sure you clearly show with delay what the outputs will be for all given inputs. You should determine the timing of your circuit by calculating the longest delay and allowing enough time for the circuit to make the transitions.

Explanation / Answer

// Verilog code for a full adder using AND, ORS, and NOTs only// module full_adder_gates(x,y,z,sum,carry); input x,y,z; output sum,carry; wire and1,and2,and3,sum1; and U_and1 (and1,x,y), U_and2 (and2,x,z), U_and3 (and3,y,z); or U_or (carry,and1,and2,and3); xor U_sum (sum,x,y,z);//xor can be made using just "and" and or gates endmodule

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