Change this verilog code to do the addition and subtraction outside of the multi

Question

Change this verilog code to do the addition and subtraction outside of the multiplexer and instead use the multiplexor to decide to show either the addition or subtraction result (1 for addition and 0 for subtraction). Make sure to use different registers for each the addition and subtraction.

Note: A and B are 4 bit inputs. S is the selector. It is to display the result in a 7 segment display.

module AddOrSubtractThenSelectAndDecodeInto7SegmentsDisplay(A,B,S,Result,Overflow,Display);

input [3:0] A;
input [3:0] B;
input S;

output reg [6:0] Display;
output reg [4:0] Result;
output reg Overflow;

always @(S or A or B)
begin:MUX
case (S)
0 : {Result} = A-B;
1 : {Result} = A+B;
endcase
end

always @(Overflow, Result) begin
if(Overflow ==1) begin
Result = 4'bx;
end
else
case (Result)
5'b0000: Display = 7'b1111110;//0
5'b0001: Display = 7'b0110000;//1
5'b0010: Display = 7'b1101101;//2
5'b0011: Display = 7'b1111001;//3
5'b0100: Display = 7'b0110011;//4
5'b0101: Display = 7'b1011011;//5
5'b0110: Display = 7'b1011111;//6
5'b0111: Display = 7'b1110000;//7
5'b1000: Display = 7'b1111111;//8
5'b1001: Display = 7'b1111011;//9
5'b1010: Display = 7'b1110111;//A
5'b1011: Display = 7'b0011111;//B
5'b1100: Display = 7'b1001110;//C
5'b1101: Display = 7'b0111101;//D
5'b1110: Display = 7'b1001111;//E
5'b1111: Display = 7'b1000111;//F
default: Display = 7'b0011101;
endcase

                  
end

  
endmodule

Explanation / Answer

Please find the Verilog Code

input [3:0] A;
input [3:0] B;
input [1:0] S;

output reg [3:0] Result;
output reg Overflow;
output reg [6:0] Display;

reg [3:0] Result_reg;

wire [3:0] A;
wire [3:0] B;
wire [1:0] S;

assign Result = (Overflow) ? 4'bx : Result_reg;

always @(A,B) begin
if (S == 0'b0)
{Overflow, Result_reg} = A - B;
else if (S == 1'b1)
{Overflow, Result_reg} = A + B;
end

always @(Overflow,Result_reg) begin
case ({Overflow, Result_reg}) inside
[5'b1000:5'b11111] : Display = 7'b0011101;
5'b00000: Display = 7'b1111110;//0
5'b00001: Display = 7'b0110000;//1
5'b00010: Display = 7'b1101101;//2
5'b00011: Display = 7'b1111001;//3
5'b00100: Display = 7'b0110011;//4
5'b00101: Display = 7'b1011011;//5
5'b00110: Display = 7'b1011111;//6
5'b00111: Display = 7'b1110000;//7
5'b01000: Display = 7'b1111111;//8
5'b01001: Display = 7'b1111011;//9
5'b01010: Display = 7'b1110111;//A
5'b01011: Display = 7'b0011111;//B
5'b01100: Display = 7'b1001110;//C
5'b01101: Display = 7'b0111101;//D
5'b01110: Display = 7'b1001111;//E
5'b01111: Display = 7'b1000111;//F
default: Display = 7'bx;
endcase
end

endmodule

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