5.15 We have seen how all RISC-style instructions can be executed using the step

Question

5.15 We have seen how all RISC-style instructions can be executed using the steps in Figure 5.4 on the multi-stage hardware of Figure 5.8. Autoincrement and Autodecrement addressing modes are not included in RISC-style instruction sets. Explain why the instruction

Load R3, (R5)+

cannot be executed on the hardware in Figure 5.8.

Step Action 1 Fetch an instruction and increment the program counter. 2 Decode the instruction and read registers from the register file. 3 Perform an ALU operation. 4 Read or write memory data if the instruction involves a memory operand. 5 Write the result into the destination register, if needed. Figure 5.4 Figure 5.4 A five-step sequence of actions to fetch and execute an instruction. stap sequence of actions to fetch and euvecute on insruction

Explanation / Answer

For our Stage 2, we need four inputs . So the first time we are not having address of C. At Stage 3, the ALU is loaded with operations from two inputs, out of which one is a
multiplexed input., based on an intermediate value.
The output from ALU is used again in a multiplexer. The ALU is already performing an action, and we cannot ask it to perfrom another action in between, hence cannot execute the
instruction Load R3, (R5)+. The ALU is still under operation with the previous values.

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