A pipelined CPU is designed to run at 500MHz (2ns per clock cycle). The table be
ID: 3677068 • Letter: A
Question
A pipelined CPU is designed to run at 500MHz (2ns per clock cycle). The table below shows required latency for executing each of the five stages (X: not needed). The designers of the machine decided to increase the maximum clock rate from 500MHz to 1GHz by adding more pipeline stages. The result is a new machine with 8 pipeline stages. The designers split stage IF into two stages, IF1 and IF2, stage EX into EX1 and EX2, and stage MEM into MEM1 and MEM2. The new machine is able to run at 1GHz with a Ins per clock cycle. Machine with 10 pipeline stages by splitting IF, EX, and MEM respectively into two separate stages. What is the maximum throughput (instructions per second) of this new 8 stage pipelined machine? (Assuming, no pipeline stall at all).Explanation / Answer
The five-stage pipeline has following steps:
IF -- instruction fetch (and PC update)
ID -- Instructions decodes (and get operands from registers)
EX -- ALU operation (can be effective address calculation)
MA -- memory access
WB -- write back (results written to register(s))
IF1 & IF2-- instruction fetch (and PC update)
ID -- Instructions decodes (and get operands from registers)
EX1 & EX2 -- ALU operation (can be effective address calculation)
MA1 & MA2 -- memory access
WB -- write back (results written to register(s))
If suppose there are 100 MIPS instructions mix with following instruction:
Throughput:
Pipeline throughput: instructions completed per second
=1instr/max[lat(IF1),lat(IF2),lat(ID),lat(EX1),lat(EX2),lat(MEM1),lat(MEM2),lat(WB)]
=1instr/max[8ns,6ns,6ns,5ns]
=1instr/10 ns (ignoring pipeline overload)
clock peroide: 13 ns
Balance the length of each pipeline stage formula is:
Throughput: Depth of the pipeline/ Time per instruction on pipelined machine
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