TASKS: 1. In a single .v file, write modules for the following state elements (U
ID: 3679761 • Letter: T
Question
TASKS:
1. In a single .v file, write modules for the following state elements (Using Verilog Code)
a. Gated RS-latch (Structural)
b. Negative edge-triggered JK Flip-Flop (Behavioral)
c. Negative edge-triggered D-Flip-Flop with asynchronous reset and synchronous enable (Behavioral)
d. A positive edge-triggered D-Flip-Flop implemented structurally in the Master-Slave pattern using D-latches (each D-latch, Behaviorally implemented).
2. Write a single testbench that goes through sufficient input patterns to showcase the behavioral differences of the above using the following paradigms (see testbench for sim3 for additional examples). Assume that the R and K inputs of elements a. and b. are the same, as are the J and S inputs. Similarly, assume that the D input is the same for c. and d. Create a module named Top that instantiates state elements a. through d. and tests them in parallel, driving their outputs to its outputs.
Testbench paradigms:
a. Clock generation via
reg clkSlow;
reg clkFast;
always #7 clkSlow = ~clkSlow;
always #2 clkFast = ~clkFast;
b. Use a behavioral unconditional modulo up-counter with reset to keep track of time:
reg [7:0] count;
always@(posedge clkFast)
begin
if (reset)
count <= 8’h00;
else
count <= count +8’h01;
end
c. Use clkSlow as the clock for all clocked/gated logic elements from task 1. Use the counter driven by clkFast and comparators to force events to happen at a specific time in the test case or directly connect bits of count to inputs
Explanation / Answer
1. a) A gated RS latch
module part1 (Clk, R, S, Q);
input Clk, R, S;
output Q;
wire R_g, S_g, Qa, Qb /* synthesis keep */ ;
and (R_g, R, Clk);
nd (S_g, S, Clk);
nor (Qa, R_g, Qb);
nor (Qb, S_g, Qa);
assign Q = Qa;
endmodule
// A gated RS latch
module part1 (Clk, R, S, Q);
input Clk, R, S;
output Q;
wire R_g, S_g, Qa, Qb /* synthesis keep */ ;
assign R_g = R & Clk;
assign S_g = S & Clk;
assign Qa = (R_g | Qb);
assign Qb = (S_g | Qa);
assign Q = Qa;
endmodule
b)JK flip flop is an edge triggered storage element, which means that data is synchronized to an active edge of clock cycle.
The active edge may be a positive or negative.
The data stored on active edge is conditional, which means it is dependent on the data present at the J and K inputs, whenever clock makes a transition at an active edge.
module jk_flip_flop(J, K, clk, Q);
input J, K, clk;
output Q;
reg Q;
reg Qm;
always @(posedge clk)
if(J == 1 && K == 0)
Qm <= 1;else
if(J == 0 && K == 1)
Qm <= 0;else
if(J == 1 && K == 1)
Qm <= ~Qm;
Q <= Qm;
endmodule
c&d) It is easy to make a D flip flop with synchronous edge triggered reset like this
2)
c)clocking cb @ (posedge clk)
default input #1ns output #1ns;
output reset_n;
output din;
output frame_n;
output valid_n;
input dout;
input busy_n;
input valido_n;
input frameo_n;
endclocking:cb
a)module Tb();
reg clock;
integer no_of_clocks;
parameter CLOCK_PERIOD = 5;
initial no_of_clocks = 0;
initial clock = 1'b0;
always #(CLOCK_PERIOD/2) clock = ~clock;
always@(posedge clock)
no_of_clocks = no_of_clocks +1 ;
initial
begin
#50000;
$display("End of simulation time is %d , total number of clocks seen is %d expected is %d",$time,no_of_clocks,($time/5));
$finish;
end
endmodule
B)
reg [7:0] count;
always@(posedge clkFast)
begin
if (reset)
count <= 8’h00;
else
count <= count +8’h01;
end
Related Questions
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.