For this problem you are to consider a forwarding unit for a 5-stage pipeline pr

Question

For this problem you are to consider a forwarding unit for a 5-stage pipeline processor. The forwarding unit returns the value to be forwarded to the current instruction. There are three places that the values for register RS and register RT can come from: decode stage (register file), memory stage, and write-back stage.

The write-back and memory stage information consists of: • _INDEX- explaining which inflight register index is to be written • _VALUE- the value that is to be written • _ENABLE- whether or not the instruction in the stage is writing. The decode stage simply states the register index (for RS and RT) and the corresponding register value from the register file. Generally three values could exist, one of which the forwarding unit should choose for each of the RS and RT register value requests. The memory stage has value MEM, the write-back stage has value WB, and the register file has value RS-REG or RT-REG. Using the table below which contains information about all of the instruction stages, indicate which value should be forwarded to the current instruction: MEM, WB, RS-REG, or RT-REG. Each line represents a Forwarding unit evaluation; there is no connection between evaluation lines in the table. You do not need to worry about hazard detection, only value bypassing.

DECODE STAGE INFORMATION RS INDE5 bits) RT NDE bits) RS RE VALUE (2b) RT REG VALIJE (32hits) MEMORY STAGE INFORMATION REGISTER NDEX5 bits VALLIT. (32 bits wRlt ENABLE (t lin) VALU 2 its) WRITE ENABLE(1 ta) VALLLE FOR T WRITE-BACK STAGE LNFORMATION

Explanation / Answer

Rs value:

RS REG
WB
RS-REG
WB
MEM

Rt value

RT-REG
RT-REG
MEM
WB
RT-REG

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