Assume Risc pipeline with five stages IF,ID,EX,MEM and WB. Consider the followin

Question

Assume Risc pipeline with five stages IF,ID,EX,MEM and WB. Consider the following program that compute the sum of 100 numbers i the memory starting from the address 1000.

Lw

Lw R1,#100 // load 100 to R1

Lw R2,#0 // load 0 to R2

Lw R3, #1000 // save the start memory address saved in R3

Loop: Lw R4,0(R3) // fetch from memory address saved in R3

Add R2,R2,R4 // increase R2 by the value of R4

Add R3,R3,#4 // increase the address by 4 for the next number

Sub R1,#1 // Decrease R1 by 1

BNEZ R1, loop // go to loop if R1 is not zero

1. Count the number of stalls in the pipeline with the current program.

2.Reduce the number of stalls by rearranging the order of the instructions in the program. Point out how to insert an instruction into the branch delay slot.

Explanation / Answer

loading 100 to register R1

loading 0 to register R2

memory address was saved in register R3

here address of R3 is saved in register R4

adding the values in R4 and R2

saving the result in R2

change the address of R3 to new address increased by 4

decreasing the value by i for R1 register

1) here the stalls are 6 because it was not multiprogramming that means no overlapping for each instruction one stall no overlapping so individual stalls only

2)last instruction to second position , no more changes can be needed this will reduce the stalls by one so final result is 5stalls

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