Write a Verilog module which accepts the clock, a reset, the immediate value fro
ID: 3684118 • Letter: W
Question
Write a Verilog module which accepts the clock, a reset, the immediate value from the instruction word (least significant byte), and the zero output from the ALU as inputs and generates an 8-bit Program Counter (PC) for the output. Note that in this architecture when we have a branch, the next PC value should be the current PC value plus the offset which is extracted from the branch instruction. The offset is represented in two's complement, so the range of branch target is from PC - 128 to PC + 127. Note that the value of PC should not exceed 0xFF as we have a 256-deep instruction memory. You do not need to check for this condition in your hardware.Explanation / Answer
1. Testing a circuit that requires a clock signal :
module pwm #(parameter CTR_LEN = 8) (
input clk,
input rst,
input [CTR_LEN - 1 : 0] compare,
output pwm
);
reg pwm_d, pwm_q;
reg [CTR_LEN - 1: 0] ctr_d, ctr_q;
assign pwm = pwm_q;
always @(*) begin
ctr_d = ctr_q + 1'b1;
if (compare > ctr_q)
pwm_d = 1'b1;
else
pwm_d = 1'b0;
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
end else begin
ctr_q <= ctr_d;
end
pwm_q <= pwm_d;
end
endmodule
2. To test this we need to write a test bench :
module pwm_tb ();
reg clk, rst;
reg [7:0] compare;
wire pwm;
pwm #(.CTR_LEN(8)) DUT (
.clk(clk),
.rst(rst),
.compare(compare),
.pwm(pwm)
);
initial begin
clk = 1'b0;
rst = 1'b1;
repeat(4) #10 clk = ~clk;
rst = 1'b0;
forever #10 clk = ~clk; // generate a clock
end
initial begin
compare = 8'd0; // initial value
@(negedge rst); // wait for reset
compare = 8'd128;
repeat(256) @(posedge clk);
compare = 8'd30;
repeat(256) @(posedge clk);
$finish;
end
endmodule
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