I\'ve got a question for my Computer Organization class that I don\'t understand

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I've got a question for my Computer Organization class that I don't understand how to work through. I've pasted it below, any help would be appreciated. Thanks!

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Suppose a processor has a special type of interrupt which is commonly known as reset interrupt. When this interrupt is received, instead of fetching the first instruction of an interrupt handler, the processor clears all its data registers, and sets the program counter (PC) to its initial value. Suppose for this problem the initial value of program counter is 0x40FF. Then it starts execution from that initial value again.

Assume that the processor checks for interrupts in the last execution step of every instruc- tion. That means after completing the operations of stage 3, if an interrupt request is present and interrupts are enabled, the request is accepted.

Give a suitable sequence of steps for performing these actions. What additional hardware is needed in Figures 5.18 to 5.20 to support this interrupt processing?

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A pdf of figure 5.18 & 5.20 can be found in this dropbox link.

https://www.dropbox.com/s/ln0dudmnn7uiu5t/%236.docx?dl=0Figure 5.20

Explanation / Answer

What is an interrupt?

            An interrupt is a dynamic event that needs prompt attention by the CPU. Usually an interrupt only needs a short period of CPU time to serve it. After that the original process can resume its execution.

            There are two types interrupting events: hardware interrupts that are those issued by I/O device controllers when they need CPU to process I/O data, and software interrupts, also called traps, that are raised when the current process executes a special trap instruction to indicate that something wrong has happened or the process needs special service from the operating system.

How to issue an interrupt request?

            There are two groups of wires of the system bus that are critical to the working of interrupt processing:

How is an interrupt request detected?

            There is a special Interrupt Enabled Bit in a system control register. If this bit carries 1, the system is ready to process interrupt requests. If this bit carries 0, the system will ignore any interrupt requests.

For the discussion of interrupt processing, the execution of an instruction has three phases:

How to find the interrupt’s handler?

            As we mentioned earlier, each type of interrupts will be processed by its own special interrupt handler. These interrupt handlers are an important component of an operating system. The starting address of each of these interrupt handlers are saved in a table called 3 an Interrupt Vector.

            The Interrupt Vector is usually stored at the lower end of the main memory, starting from address 0. Suppose an I/O device has ID 3, then the starting address of its interrupt handler is in memory address 3

Upon entering the interrupt processing phase, the following events will happen:

What will the interrupt handler do?

The interrupt handler will do the following steps:

The following steps are explain easily, what are explained in above sentences.

The sequence of events when an interrupt happens is:

We have to add context switch with previous diagram:

a context switch is the process of storing and restoring the state (more specifically, the execution context) of a process or thread so that execution can be resumed from the same point at a later time.

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