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In class, we discussed that using a CLK input to the basic S-R latch serves as a

ID: 3686471 • Letter: I

Question

In class, we discussed that using a CLK input to the basic S-R latch serves as a "gate" which allows changes to latch state (Q output) only when CLK = 1 (latch is OPEN). This new circuit is a clocked SR latch (Lecture 23 - Slides 6, 7, 8, and 9). The characteristic table of a clocked SR latch also has the undesirable inputs (R = 1, S = 1) which results in an oscillatory condition at Q output (slide 7). Draw the timing diagram for the clocked SR latch (refer to the circuit in slide 7) when the input is changed from R = 1, S = 1 to R = 0, S = 0 at the negative edge of the clock for each of the three cases below. The period of CLK is 2ns. Assume all gates have a delay of 1 ns. Assume AND gates have a delay of Ins. The Q-NOR gate has a delay of 1 ns and the Q-NOR gate has a delay of 2 ns. Assume AND gates have a delay of Ins. The Q-NOR gate has a delay of 2 ns and the Q-NOR gate has a delay of 1 ns. Summarize your observations from the timing diagrams of,b,c and reason why the input R = 1, S = 1 is un-desirable.

Explanation / Answer

The SR (Set-Reset) flip-flop is one of the simplest sequential circuits and consists of two gates connected output of each gate is connected to one of the inputs of the other gate, giving a form of positive feedback or ‘cross-coupling’. The circuit has two active low inputs marked S and R, ‘NOT’ being indicated by the bar above the letter, as well as two outputs, Q and Q.

A bistable multivibrator has two stable states, as indicated by the prefix bi in its name. Typically, one state is referred to as set and the other as reset. The simplest bistable device, therefore, is known as a set-reset, or S-R, latch.

The Q and not-Q outputs are supposed to be in opposite states. I say “supposed to” because making both the S and R inputs equal to 1 results in both Q and not-Q being 0. For this reason, having both S and R equal to 1 is called an invalid or illegal state for the S-R multivibrator. Otherwise, making S=1 and R=0 “sets” the multivibrator so that Q=1 and not-Q=0. Conversely, making R=1 and S=0 “resets” the multivibrator in the opposite state. When S and R are both equal to 0, the multivibrator’s outputs “latch” in their prior states. Note how the same multivibrator function can be implemented in ladder logic.

If a circuit has only combinational devices (e.g. gates like AND, OR,MUX(s), etc.)and no Memory elements then it is a Combinational circuit.If the circuit has memory elements such as Flip Flops, Registers, Counters, or other state devices then it is a Sequential Circuit. Synchronous sequential circuits will also have a clearly labeled clock input

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