Please copy-paste the following chunks of code into two new sources respectively
ID: 3689027 • Letter: P
Question
Please copy-paste the following chunks of code into two new sources respectively (put the module into a "Verilog Module", and the test bench into a "Verilog Test Fixure") in Xilinx ISE. Then observe the values printed in the console to understand how "{overflowOfAddition,resultOfAddition} = X + Y;" works.
Please complete the table below.
//----- "Verilog Module" code: module addition( input [1:0] X, input [1:0] Y, output [1:0] resultOfAddition, output overflowOfAddition ); reg [1:0] resultOfAddition; reg overflowOfAddition; always @ (X, Y)begin {overflowOfAddition,resultOfAddition} = X + Y; end endmodule
?//----- "Verilog Test Fixure" code: module additionTestBench; // Inputs reg [1:0] X; reg [1:0] Y; // Outputs wire [1:0] resultOfAddition; wire overflowOfAddition; // Instantiate the Unit Under Test (UUT) addition uut ( .X(X), .Y(Y), .resultOfAddition(resultOfAddition), .overflowOfAddition(overflowOfAddition) ); integer i; integer j; initial begin $monitor("X=%d Y=%d overflowOfAddition=%d resultOfAddition=%d", X, Y, overflowOfAddition, resultOfAddition); X = 3; Y = 3; #100; for(i=0; i<=3; i=i+1) begin X = X+1; for(j=0; j<=3; j=j+1) begin Y= Y+1; #50; end end end endmodule //----- end of code
XYverflowOfAddition resultOfAddition 0 2 0 2 O 0 3 0 110 210 221 2 21 2 3 2 31 30 3 21 3 13Explanation / Answer
a) when the variable x = 1 and y = 3 the overflowOfAddition = 1 and the result = 0
b) when the variable x = 3 and y = 3 the overflowOfAddition = 1 and the result = 2
table is appended with the values:
X
Y
overflowOfAddition
resultOfAddition
0
0
0
0
0
1
0
1
0
2
0
2
0
3
0
3
1
0
0
1
1
1
0
2
1
2
0
3
1
3
1
0
2
0
0
2
2
1
0
3
2
2
1
0
2
3
1
1
3
0
0
3
3
1
1
0
3
2
1
1
3
3
1
2
X
Y
overflowOfAddition
resultOfAddition
0
0
0
0
0
1
0
1
0
2
0
2
0
3
0
3
1
0
0
1
1
1
0
2
1
2
0
3
1
3
1
0
2
0
0
2
2
1
0
3
2
2
1
0
2
3
1
1
3
0
0
3
3
1
1
0
3
2
1
1
3
3
1
2
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