1). Match the terms below with the explanations which follow. (a) cache hit (b)
ID: 3689722 • Letter: 1
Question
1). Match the terms below with the explanations which follow.
(a) cache hit (b) cache line fill (c) write hit
1.___ The processor attempts to write an operand to a cacheable area of memory, and a valid cache line exists for that memory address, the processor can write into the cache instead of writing it to system memory.
2.___ The memory location containing that operand is still cached the next time the processor attempts to access the operand, and the processor can read the operand from the cache instead of going back to memory.
3.___ When the processor recognizes that an operand being read from memory is cacheable, the processor reads an entire cache line into the appropriate cache.
2). The procedure when one processor (A) attempts to find out if another processor (B) has cached a memory location which A requires is called:
a. data coherency check c. snooping
b. read misses d. write hits
3).IA-32 and Intel 64 processors use the MESI (modified, exclusive, shared, invalid) cache protocol to maintain consistency with internal caches and caches in other processors. circle) In which of the MESI states (modified, exclusive, shared, invalid) can a cache line also be present in another processor's cache?
4). Refer to the instruction descriptions in Volume 2. Which instructions move data into level 1 cache?
Explanation / Answer
1)
1) The processor attempts to write an operand to a cacheable area of memory, and a valid cache line exists for that memory address, the processor can write into the cache instead of writing it to system memory. - cache hit - Option A
2) The memory location containing that operand is still cached the next time the processor attempts to access the operand, and the processor can read the operand from the cache instead of going back to memory. - cache hit - Option A
3) When the processor recognizes that an operand being read from memory is cacheable, the processor reads an entire cache line into the appropriate cache. - cache line fill - Option B
2) The procedure when one processor (A) attempts to find out if another processor (B) has cached a memory location which A requires is called: - data coherency check - Option A
3)
Every cache line is marked with one of the four following states:
Modified
The cache line is present only in the current cache, and is dirty; it has been modified from the value in main memory. The cache is required to write the data back to main memory at some time in the future, before permitting any other read of the (no longer valid) main memory state. The write-back changes the line to the Shared state.
Exclusive
The cache line is present only in the current cache, but is clean; it matches main memory. It may be changed to the Shared state at any time, in response to a read request. Alternatively, it may be changed to the Modified state when writing to it.
Shared
Indicates that this cache line may be stored in other caches of the machine and is clean; it matches the main memory. The line may be discarded (changed to the Invalid state) at any time.
Invalid
Indicates that this cache line is invalid (unused).
So the answer is clear that the state SHARED can have a cache line also be present in another processor's cache.
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