While executing the following instructions, a pre-fetch abort exception occurs.

Question

While executing the following instructions, a pre-fetch abort exception occurs. When the processor starts to service the exception, the ADD instruction had been fetched and was in the process of being executed. The values of registers r0, r8, r13, r14, and the CPSR arc 0x000000A6, 0xFFFF89E1, 0xFFFA0040 0x000022A0, and x90000052, respectively. You may assume that the ADD instruction is stored at memory address 0x00009408.

ADD rs, rs, r4

CMP r2, rS

BEQ increment

a.When the exception handling routine starts, give the content of r0, r8, rl3 r14 the CPSR, and Pre_SPSR?

b. After the pre-fetch service routine is serviced, which instruction should be fetched immediately following the return from the handler? What are the values in r0, r8, rI3, rl4. and the CPSR after the exception is serviced, but BEFORE the instruction after the handler instruction is fetched?

Explanation / Answer

In the case of exception handling in the ARM systems, the register in use moves from the
user mode to FIQ mode.
The address in the FIQ mode after the interrupt is always 'PC+4'.
Thus for the data registers, we will have values as:-

r0 = 0xFFFF89E1
r8 = 0xFFFA0040+4
r13 = 0xFFFA0040+4
r14 = 0x000022A0 +4
CSPR = 0x90000052
The value of the link register will always be the same as the previous one.

2)After the pre fetch servode routine is fetched, the instruction for incrementing the counter i.e
"BEQ increment" will be fetched immediately, after returning from the handler.

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