REGISTER TRANSFER LEVEL Using Modelsim write a Verilog program that will demonst
ID: 3691445 • Letter: R
Question
REGISTER TRANSFER LEVEL
Using Modelsim write a Verilog program that will demonstrate each part. For each part, include a snip of the associated module, a snip of the output statements located in the Transcript box. When making these statements, use sufficient text to clearly identify which operation you are doing, what the variables are as well as the results of the operations.
Part 1) Blocking/nonblocking: Write a module using Verilog which will clearly demonstrate the difference between blocking and nonblocking procedural assignments.
Part 2) Arithmetic: Write a module using Verilog which demonstrates the arithmetic operators +, -, *, /, %, and ** When ever possible, use the same variables in the different operations.
Part 3) Bitwise or Reduction: Write a module using Verilog which demonstrates the following operators; ~, &, ~&, ^, and ~| When ever possible, use the same variables in the different operations.
Part 4) Shift: Write a module using Verilog which demonstrates the following operators; >>, <<, >>>, and {,} When ever possible, use the same variables in the different operations.
Part 5) Relational: Write a module using Verilog which demonstrates the following operators; >, ==, !=, ===, >=, <= When ever possible, use the same variables in the different operations.
All five parts of this assignment should be stand alone programs in their own separate files. Do not incorporate multiple parts into the same module.
Explanation / Answer
module blocking (cl,x,y);
input cl;
input x;
output y;
wire cl;
wire x;
reg y;
reg z;
always @ (posedge cl)
begin
z = x;
y = z;
end
endmodule
module nonblocking (cl,x,y);
input cl;
input x;
output y;
wire cl;
wire x;
reg y;
reg z;
always @ (posedge cl )
begin
z<= x;
y <= z;
end
endmodule
module Arith (x,y, a, b, c, d, e);
input [2:0] x, y;
output [3:0] a;
output [4:0] c;
output [2:0] b, d, e;
reg [3:0] a;
reg [4:0] c;
reg [2:0] b, d, e;
always @(x or y)
begin
a=x+y;//addition
b=x-y;//subtraction
c=x*y;//multiplication
d=x/y;//division
e=x%y;//modulus of A divided by B
end
endmodule
module Relation(x, y, a, b, c, d);
input [2:0] x, y;
output a, b, c, d;
reg a, b, c, d;
always @(x or y)
begin
a=x<y;//less than
b=x<=y;//less than or equal to
c=x>y;//greater than
if (x>y)
d=1;
else
d=0;
end
endmodule
module Shift (x, a, b);
input [7:0] x;
output [7:0] a, b;
parameter y=3; reg [7:0] a, b;
always @(x)
begin
a=x<<y; //logical shift left
b=x>>y; //logical shift right
end
endmodule
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