1. What is the difference between DRAM and SRAM, in terms of characteristics suc

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Question

1. What is the difference between DRAM and SRAM, in terms of characteristics such as speed, size and cost? 2. List and briefly define three techniques for performing I/O (i.e., communicating between the processor and I/O devices). 3. What is the difference between memory-mapped I/O and the Isolated I/O (i.e., I/O Addressing Independent of Memory)? 4. When an interrupt occurs, how does the processor identifies which device issued the interrupt? 5. When a DMA module takes control of a bus, and while it retains control of the bus, what does the processor do? Homework Assignment #5 Dr. Hatfield 6. What is the minimal address bits for a 512MB memory? What about a 24GB memory? 7. Provide a short description and definition for each of the following non-volatile memory technologies Drum memory Magnetic core memory Bubble memory Flash memory Static RAM (SRAM) Dynamic RAM (DRAM) Synchronous DRAM (SDRAM) Cache DRAM (CDRAM) RamBus DRAM (RDRAM) DDR SDRAM PRAM RRAM Millipede 8. The input status bit in an interface circuit, which indicates that new data are available, is cleared as soon as the input data register is read. Why is this important?

Explanation / Answer

Differences between DRAM and SRAM:-

DRAM (Dynamic Random Access Memory):

DRAM requires the data to be refreshed periodically in order to retain the data.

DRAM module only needs a transistor and a capacitor for every bit of data.

DRAM module can have almost 6 times more capacity with a similar transistor count to an SRAM module.

DRAM memory is slower and less desirable than SRAM.

One complication is the much higher power used by DRAM memory, this difference is very significant in battery powered devices.

DRAM is less expensive.

DRAM is used in main memory.

SRAM (Static Random Access Memory)

SRAM does not need to be refreshed as the transistors inside would continue to hold the data as long as the power supply is not cut off.

SRAM needs a lot more transistors in order to store a certain amount of memory.

SRAM modules are also much simpler compared to DRAM, which makes it easier for most people to create an interface to access the memory. This makes it easier to work with for hobbyists and even for prototyping.

SRAM is more expensive.

SRAM is used in cache memory.

The three techniques for performing I/O:

Memory-mapped I/O uses the same address bus to address both memory and I/O devices, the memory and registers of the I/O devices are mapped to address values. So when an address is accessed by the CPU, it may refer to a portion of physical RAM, but it can also refer to memory of the I/O device.

Programmed input/output (PIO) is a method of transferring data between the CPU and a peripheral, such as a network adapter or an ATA storage device

Interrupt I/O it is the way of controlling input/output activity in which a peripheral or terminal that needs to make or receive a data transfer sends a signal that causes a program interrupt to be set. At a time appropriate to the priority level of the I/O interrupt, relative to the total interrupt system.

Direct memory access (DMA) is a feature of computer systems that allows certain hardware subsystems to access main system memory(RAM) independently of the central processing unit (CPU).

Difference between memory-mapped I/O and the Isolated I/O (i.e., I/O Addressing Independent of Memory)

Isolated I/O

No.

Memory Mapped I/O

Isolated I/O uses separate memory space.

Memory mapped I/O uses memory from the main memory.

Limited instructions can be used. Those are IN, OUT, INS, OUTS.

Any instruction which references to memory can be used.

The addresses for Isolated I/O devices are called ports.

Memory mapped I/O devices are treated as memory locations on the memory map.

IORC & IOWC signals expands the circuitry.

IORC & IOWC signals has no functions in this case which reduces the circuitry.

When an interrupt occurs, how does the processor identifies which device issued the interrupt?

When you hit interrupt through keyboard it will be initially sent to PIC then PIC sends a signal on INT pin of processor ( due to which processor will aware that there is something interrupt due to some device ) , when processor will free it will send READY signal to PIC then PIC sends information regarding interrupt device and interrupt type to processor via data bus line and finally interrupt is executed.

There are various types of interrupts which have different priorities e.g. your keyboard interrupt have higher priority than auto run interrupt of pen drive. And for controlling interrupts according to their priorities there total 8 levels of priority in PIC.

When a DMA module takes control of a bus, and while it retains control of the bus, what does the processor do?

If you have a 'real' DMA, the DMA is a peripheral which does not interact or interfere with any other part of the microprocessor or microcontroller, including the main bus. All the ARM processors I have worked with are like this.

Some low-power or low-cost microprocessors and microcontrollers have a feature which they also call a DMA, but which is occupies the bus and prevents the processor core from doing anything else. I believe that these have been implemented by various different methods, and even though they do prevent any other core activity, these DMAs are still useful. Some small, low power uC I have worked with have this.

Either way, the DMA is useful because they can transfer data much more quickly than is possible in software, especially for large collections of data, such as arrays of ADC samples. The DMA is also useful because you can pre-configure it, and allow for hardware or software triggering, which is great for using on quick, time sensitive, periodic, or unpredictable events.

What is the minimal address bits for a 512MB memory? What about a 24GB memory?

You need log2(n) bits to address n bytes. For example, you can store 256 different values in an 8 bit number, so 8 bits can address 256 bytes. 210 = 1024, so you need 10 bits to address every byte in a kilobyte. Likewise, you need 20 bits to address every byte in a megabyte, and 30 bits to address every byte in a gigabyte. 232 = 4294967296, which is the number of bytes in 4 gigabytes, so you need a 32 bit address for 4 GB of memory.

Short notes on non-volatile technologies :

Core uses tiny magnetic toroids (rings), the cores, through which wires are threaded to write and read information. Each core represents one bit of information. The cores can be magnetized in two different ways and the bit stored in a core is zero or one depending on that core's magnetization direction. The wires are arranged to allow for an individual core to be set to either a one or a zero and for its magnetization to be changed by sending appropriate electric current pulses through selected wires. The process of reading the core causes the core to be reset to a zero, thus erasing it. This is called destructive readout. When not being read or written, the cores maintain the last value they had, even when power is turned off. This makes them nonvolatile.

Bubble memory :